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US 6,943,610 B2Granted
Clock distribution network using feedback for skew compensation and jitter filtering
AssigneeIntel Corporation
InventorMartin Saint-Laurent
Life of this patent
Estimating the term…
Abstract
A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering. In an embodiment, a number of clock processor nodes are distributed throughout the clock distribution network on the IC at respective local clock regions. A master clock generator generates a master clock for distribution to the clock processor nodes, via the clock distribution network, to compensate clock skew and filter clock jitter locally at the respective local clock regions.
Claims48
An architecture for clock distribution on an integrated circuit (IC), comprising:
- a clock distribution network;
- a plurality of clock processor nodes distributed throughout the clock distribution network on the IC at respective local clock regions;
- and
- a master clock generator to generate a master clock for distribution to the clock processor nodes, via the clock distribution network, to compensate clock skew and filter clock jitter locally at the respective local clock regions;
- and
- wherein:
- the master clock generator corresponds to a master phase-locked loop (PLL) to generate and keep the master clock synchronized responsive to a system clock;
- and
- each clock processor node at each local clock region comprises:
- a slave phase-locked loop (PLL) to attenuate the clock jitter from the master clock introduced by the clock distribution network;
- and
- a variable-delay element (VDE) to compensate the clock skew from the master clock introduced by the clock distribution network.
9 more elements
A clock distribution network for an integrated circuit (IC) chip, comprising:
- an array of phase-locked loops (PLLs) at clock processor nodes distributed at respective local clock regions on the IC chip, and variable-delay elements (VDE) coupled to the PLLs to compensate clock skew and enable the PLLs to filter clock jitter;
- and
- a master clock generator to generate a master clock for distribution to the clock processor nodes to enable the PLLs and VDEs to compensate clock skew and filter clock jitter locally at the respective local clock regions on the IC chip.
A method for clock distribution in an integrated circuit (IC) chip, comprising:
- generating a master clock;
- distributing the master clock to an array of phase-locked loops (PLLs) at clock processor nodes distributed at respective local clock regions on the IC chip via a clock distribution network;
- and
- performing clock skew compensation locally using variable-delay elements (VDE), and performing clock jitter filtering using the PLLs at respective clock processor nodes distributed at the respective local clock regions on the IC chip.
1 more element
A system, comprising:
- a data input device;
- a data output device;
- and
- a processor coupled to the data input device and the data output device, the processor including an array of phase-locked loops (PLLs) at clock processor nodes distributed at respective local clock regions on the processor, and variable-delay elements (VDE) coupled to the PLLs to compensate clock skew and enable the PLLs to filter clock jitter;
- and a master clock generator to generate a master clock for distribution to the clock processor nodes to enable the PLLs and VDEs to compensate clock skew and filter clock jitter locally at the respective local clock regions on the processor.
2 more elements
A system, comprising:
- a data input device;
- a data output device;
- a flash device;
- and
- a processor coupled to the data input device, the flash device, and the data output device, the processor including an array of phase-locked loops (PLLs) at clock processor nodes distributed at respective local clock regions on the processor, and variable-delay elements (VDE) coupled to the PLLs to compensate clock skew and enable the PLLs to filter clock jitter;
- and a master clock generator to generate a master clock for distribution to the clock processor nodes to enable the PLLs and VDEs to compensate clock skew and filter clock jitter locally at the respective local clock regions on the processor.
3 more elements
An architecture for clock distribution on an integrated circuit (IC), comprising:
- a clock distribution network;
- a plurality of clock processor nodes distributed throughout the clock distribution network on the IC at respective local clock regions;
- a master clock generator to generate a master clock for distribution to the clock processor nodes, via the clock distribution network, to compensate clock skew and filter clock jitter locally at the respective local clock regions;
- and
- wherein:
- the master clock generator corresponds to a master phase-locked loop (PLL) to generate and keep the master clock synchronized responsive to a system clock;
- the clock distribution network corresponds to an equal length H-tree clock distribution network in which the master clock generated from the master PLL is routed to each of the clock processor nodes of an equal distance from the master PLL, via intermediate nodes of an equal distance from the master PLL;
- and
- each clock processor node at each local clock region comprises:
- a slave phase-locked loop (PLL) to attenuate the clock jitter from the master clock introduced by the clock distribution network;
- and
- a variable-delay element (VDE) to compensate the clock skew from the master clock introduced by the clock distribution network.
9 more elements
Dependencies are inferred from the claim text.