Processing method, chip set and controller for supporting message signaled interrupt

A message signaled interrupt controller, applied to a system that comprises a chip set, a PCI bus and a system memory, wherein the chip set is coupled to the PCI bus and the system memory and includes a dynamic random access memory controller, a CPU interface and an interrupt controller, the message signaled interrupt controller comprising:

• a message signaled interrupt detector, coupled to the PCI bus and the dynamic random access memory controller to monitor a memory write transaction of the PCI bus, and when an address of the memory write transaction falls within a reserved interrupt address, a system specified message is written to the system memory via the dynamic random access memory controller and a message signaled interrupt acknowledging signal is output;
• a message signaled interrupt calculator, coupled to the message signaled interrupt detector and the CPU interface to receive and count the message signaled interrupt acknowledging signal and to form an interrupt counting value, converting the interrupt counting value into a sent interrupt counting value, and outputting the sent interrupt counting value;
• and
• a message signaled interrupt generator, coupled to the message signaled interrupt calculator and the interrupt controller, to generate a message signaled interrupt request signal to the interrupt controller, so as to enable the interrupt controller to generate an interrupt request signal;
• wherein
• the reserved interrupt address is located in the system memory.

A chip set of supporting message signaled interrupt, the chip set being coupled to a PCI bus, a central processing unit and a system memory, and the chip set comprising:

• a dynamic random access memory controller, coupled to the system memory to control and access the system memory;
• a CPU interface, coupled to the central processing unit as a control interface between the chip set and the central processing unit;
• an interrupt controller, coupled to the CPU interface to generate an interrupt request signal to the central processing unit, and to enable the central processing unit to initiate an interrupt service routine;
• and
• a message signaled interrupt controller, coupled to the PCI bus, the dynamic random access memory controller, the CPU interface and the interrupt controller to monitor a memory write transaction of the PCI bus, when an address of the memory write transaction falls into a reserved interrupt address, a system specified message is written into the system memory via the dynamic random access memory controller, and a message signaled interrupt request signal is output to enable the interrupt controller to generate the interrupt request signal;
• wherein the reserved interrupt address is located in an address of the system memory,
• wherein the message signaled interrupt controller comprises:
• a message signaled interrupt detector, coupled to the PCI bus and the dynamic random access memory controller to monitor the memory write transaction, and when the address specified in the interrupt message of the memory write transaction falls into the reserved interrupt address, the system specified message is written into the system memory via the dynamic random access memory controller and a message signaled interrupt acknowledging signal is output;
• a message signaled interrupt calculator, coupled to the message signaled interrupt detector and the CPU interface to receive and count the message signaled interrupt acknowledging signal to form an interrupt counting value, and to convert the interrupt counting value into a sent interrupt counting value, and to output the sent interrupt counting value according to the motherboard interface;
• and
• a message signaled interrupt generator, coupled to the message signaled interrupt calculator and the interrupt controller, to generate the message signaled interrupt request signal to the interrupt controller according to the interrupt counting value, and to enable the interrupt controller to generate the interrupt request signal.

A processing method of supporting message signaled interrupt, applied to a chip set which is coupled to a PCI bus and a system memory, the processing method comprising:

• monitoring a memory write transaction whose address falls into a reserved interrupt address located in the system memory;
• and
• performing an interrupt sequence when the monitored memory write transaction is sent on the PCI bus,
• wherein the chip set is coupled to a central processing unit, and the interrupt sequence includes the following steps:
• writing a system specified message of an interrupt message to the system memory according to the interrupt message of the memory write transaction;
• adding an interrupt counting value after the system specified message is written into the system memory;
• generating an interrupt request to the central processing unit according to the interrupt counting value;
• and
• activating an interrupt service routine by the central processing unit.