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US 6,940,356 B2Granted
Circuitry to reduce PLL lock acquisition time
AssigneeFairchild Semiconductor Corporation
InventorsJames J. McDonald, II, Ronald B. Hulfachor
Life of this patent
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AssigneeFairchild Semiconductor Corporation
InventorsJames J. McDonald, II, Ronald B. Hulfachor
Estimating the term…
A phase locked loop, PLL, is described with multiple parallel charge pumps that are selectively disabled as phase lock is approached. A lock detection circuit is described that enabled reference currents to be fed to the parallel charge pumps. The error signal from a phase detector is arranged as UP and a DOWN signals that are averaged in the lock detector. When the average error is large, all the reference currents feed the charge pumps that provide a high loop gain to reduce the lock time. As the lock becomes closer selective reference currents are disabled to reduce loop gain so that a smooth transition to lock is made. Selectively switching currents into a low pass filter that usually follows a charge pump in a PLL circuit automatically reduces switching noise by the operation of the low pass filter.
A phase locked loop (PLL) circuit comprising:
A phase locked loop that includes a phase detector providing an error signal to a charge pump, wherein the charge pump in response outputs a current into a low pass filter that outputs a signal to a voltage controlled oscillator, whose output is divided thereby producing a feedback signal that is compared to an input signal in the phase detector, further comprising a lock detector that provides a coarse lock signal indicating that a coarse lock state has been reached for the PLL, and at least one additional charge pump that defines an output current into the low pass filter, the additional charge pump accepts and is controlled on or off by the coarse lock signal, wherein when the additional charge pump is off the loop bandwidth of the phase locked loop is lowered.
A method of operating a phase locked loop, wherein the loop contains a low pass filter with an output driving a voltage controlled oscillator that outputs a signal that is divided forming a feedback and fed back to a phase detector that compares the feedback signal to an input signal, the phase detector outputting an error signal, wherein the error signal ultimately drives a current via multiple charge pumps into the low pass filter, the method comprising the steps of:
Dependencies are inferred from the claim text.