Method and apparatus for power management of graphics processors and subsystems that allow the subsystems to respond to accesses when subsystems are idle

A processing device, including:

• at least two subsystems, including a first subsystem and a second subsystem;
• subsystem clock circuitry including at least a first subsystem clock branch coupled and configured to assert a first subsystem clock to the first subsystem and a second subsystem clock branch coupled and configured to assert a second subsystem clock to the second subsystem;
• and
• control circuitry coupled to the subsystem clock circuitry, wherein the control circuitry and the subsystem clock circuitry are configured to operate in a subsystem clock management mode in which the control circuitry prevents the first subsystem clock branch from asserting the first subsystem clock to the first subsystem when said first subsystem is idle, and the control circuitry prevents the second subsystem clock branch from asserting the second subsystem clock to the second subsystem when said second subsystem is idle;
• multiplexing circuitry having inputs coupled to a first node at which a host clock is asserted and a second node at which a first device clock is asserted, and having at least one output coupled to the subsystem clock circuitry,
• wherein the control circuitry and the multiplexing circuitry are configured to operate in a mode in which the control circuitry causes the multiplexing circuitry to assert a selected one of the host clock and the first device clock to the subsystem clock circuitry, and wherein the first subsystem clock branch asserts the first subsystem clock to the first subsystem in response to said selected one of the host clock and the first device clock, and the second subsystem clock branch asserts the second subsystem clock to the second subsystem in response to said selected one of the host clock and the first device clock.

A processing device, including:

• at least two subsystems, including a first subsystem and a second subsystem;
• subsystem clock circuitry including at least a first subsystem clock branch coupled and configured to assert a first subsystem clock to the first subsystem and a second subsystem clock branch coupled and configured to assert a second subsystem clock to the second subsystem;
• and
• control circuitry coupled to the subsystem clock circuitry, wherein the control circuitry and the subsystem clock circuitry are configured to operate in a subsystem clock management mode in which the control circuitry prevents the first subsystem clock branch from asserting the first subsystem clock to the first subsystem when said first subsystem is idle, and the control circuitry prevents the second subsystem clock branch from asserting the second subsystem clock to the second subsystem when said second subsystem is idle;
• a host slave bus, wherein each of the first subsystem and the second subsystem includes a host register connected along the host slave bus;
• and
• a host slave unit coupled to the host slave bus, and configured to be coupled to a system bus so as to provide an interface between the system bus and the host slave bus.

A graphics processing device, including:

• at least two subsystems, including a first subsystem and a second subsystem;
• subsystem clock circuitry including at least a first subsystem clock branch coupled and configured to assert a first subsystem clock to the first subsystem and a second subsystem clock branch coupled and configured to assert a second subsystem clock to the second subsystem;
• multiplexing circuitry having inputs coupled to a first node at which a host clock is asserted and a second node at which a first device clock is asserted, and having at least one output coupled to the subsystem clock circuitry;
• control circuitry coupled to the subsystem clock circuitry and to the multiplexing circuitry;
• a host slave bus, wherein each of the first subsystem and the second subsystem includes a host register connected along the host slave bus;
• and
• a host slave unit coupled to the host slave bus, and configured to be coupled to a system bus so as to provide an interface between the system bus and the host slave bus,
• wherein the control circuitry includes a host register array connected along the host slave bus, the control circuitry is configured to operate in a subsystem clock management mode in response to a first set of control bits in a first host register of the host register array, and the control circuitry is configured to operate in a device clock management mode in response to a second set of control bits in a second host register of the host register array.

A system, including:

• a system bus;
• a CPU connected along the system bus;
• and
• a graphics processing device connected along the system bus, wherein the graphics processing device includes:
• at least two subsystems, including a first subsystem and a second subsystem;
• subsystem clock circuitry including at least a first subsystem clock branch coupled and configured to assert a first subsystem clock to the first subsystem and a second subsystem clock branch coupled and configured to assert a second subsystem clock to the second subsystem;
• and
• control circuitry-coupled to the subsystem clock circuitry, wherein the control circuitry and the subsystem clock circuitry are configured to operate in a subsystem clock management mode in which the control circuitry prevents the first subsystem clock branch from asserting the first subsystem clock to the first subsystem when said first subsystem is idle, the control circuitry prevents the second subsystem clock branch from asserting the second subsystem clock to the second subsystem when said second subsystem is idle;
• and
• wherein the control circuitry is further configured to cause either of the first or second subsystems to respond to an access even though the first or second subsystem is idle.

A system, including:

• a system bus;
• a CPU connected along the system bus;
• and
• a graphics processing device connected along the system bus, wherein
• the graphics processing device includes:
• at least two subsystems, including a first subsystem and a second subsystem;
• subsystem clock circuitry including at least a first subsystem clock branch coupled and configured to assert a first subsystem clock to the first subsystem and a second subsystem clock branch coupled and configured to assert a second subsystem clock to the second subsystem;
• and
• control circuitry coupled to the subsystem clock circuitry, wherein the control circuitry and the subsystem clock circuitry are configured to operate in a subsystem clock management mode in which the control circuitry prevents the first subsystem clock branch from asserting the first subsystem clock to the first subsystem when said first subsystem is idle, the control circuitry prevents the second subsystem clock branch from asserting the second subsystem clock to the second subsystem when said second subsystem is idle;
• a host slave bus, wherein each of the first subsystem and the second subsystem includes a host register connected along the host slave bus;
• and
• a host slave unit coupled between the host slave bus and the system bus so as to provide an interface between the system bus and the host slave bus.

A system, including:

• a system bus;
• a CPU connected along the system bus;
• and
• a graphics processing device connected along the system bus, wherein
• the graphics processing device includes;
• at least two subsystems, including a first subsystem and a second subsystem;
• subsystem clock circuitry including at least a first subsystem clock branch coupled and configured to assert a first subsystem clock to the first subsystem and a second subsystem clock branch coupled and configured to assert a second subsystem clock to the second subsystem;
• and
• control circuitry coupled to the subsystem clock circuitry, wherein the control circuitry and the subsystem clock circuitry are configured to operate in a subsystem clock management mode in which the control circuitry prevents the first subsystem clock branch from asserting the first subsystem clock to the first subsystem when said first subsystem is idle, the control circuitry prevents the second subsystem clock branch from asserting the second subsystem clock to the second subsystem when said second subsystem is idle;
• host clock generation circuitry configured to generate a host clock;
• device clock generation circuitry configured to generate at least one device clock including a first device clock;
• and
• multiplexing circuitry having inputs coupled to the host clock generation circuitry and the device clock generation circuitry, and having at least one output coupled to the subsystem clock circuitry,
• wherein the control circuitry and the multiplexing circuitry are configured to operate in a mode in which the control circuitry causes the multiplexing circuitry to assert a selected one of the host clock and the first device clock to the subsystem clock circuitry, and wherein the first subsystem clock branch asserts the first subsystem clock to the first subsystem in response to said selected one of the host clock and the first device clock, and the second subsystem clock branch asserts the second subsystem clock to the second subsystem in response to said selected one of the host clock and the first device clock.

A system, including:

• a system bus;
• a CPU connected along the system bus;
• and
• a graphics processing device connected along the system bus, wherein the graphics processing device includes:
• at least two subsystems, including a first subsystem and a second subsystem;
• subsystem clock circuitry including at least a first subsystem clock branch coupled and configured to assert a first subsystem clock to the first subsystem and a second subsystem clock branch coupled and configured to assert a second subsystem clock to the second subsystem;
• multiplexing circuitry having inputs coupled to a first node at which a host clock is asserted and a second node at which a first device clock is asserted, and having at least one output coupled to the subsystem clock circuitry;
• control circuitry coupled to the subsystem clock circuitry and to the multiplexing circuitry;
• a host slave bus, wherein each of the first subsystem and the second subsystem includes a host register connected along the host slave bus;
• and
• a host slave unit coupled to the host slave bus, and configured to be coupled to a system bus so as to provide an interface between the system bus and the host slave bus,
• wherein the control circuitry includes a host register array connected along the host slave bus, the control circuitry is configured to operate in a subsystem clock management mode in response to a first set of control bits in a first host register of the host register array, and the control circuitry is configured to operate in a device clock management mode in response to a second set of control bits in a second host register of the host register array.

A graphics processing device, including:

• at least two subsystems, including a first subsystem and a second subsystem;
• subsystem clock circuitry including at least a first subsystem clock branch coupled and configured to assert a first subsystem clock to the first subsystem and a second subsystem clock branch coupled and configured to assert a second subsystem clock to the second subsystem;
• and
• control circuitry coupled to the subsystem clock circuitry, wherein the control circuitry and the subsystem clock circuitry are configured to operate in a subsystem clock management mode in which the control circuitry prevents the first subsystem clock branch from asserting the first subsystem clock to the first subsystem when said first subsystem is idle, and the control circuitry prevents the second subsystem clock branch from asserting the second subsystem clock to the second subsystem when said second subsystem is idle;
• a system bus;
• a CPU connected along the system bus;
• the graphics processing device being connected along the system bus;
• and
• at least one input device connected along the system bus,
• wherein the CPU and the graphics processing device are configured to operate in a frame generation mode in which frames of image data are generated by the graphics processing device at a selected frame rate, the selected frame rate is a selected one of a set of predetermined frame rates, and the CPU is configured to respond to control data asserted from the input device over the system bus by causing the device to enter the frame generation mode, where the control data determines the selected frame rate.