US 6,934,900 B1 · Test pattern generator for SRAM and DRAM

Abstract

A test pattern generation and comparison circuit creates test pattern stimulus signals for and evaluates response signals from logic or memory such as random access memory (RAM). It utilizes both parallel and serial interfaces to the logic/memory under test. The test pattern generation and comparison circuit further provides a method for testing logic and memory utilizing built-in self test (BIST) techniques. The method uses a programmable logic/memory commands which are translated into physical logic signals and timings for the logic or memory under test. The results of the test pattern generated and applied to the logic or memory are compared to expected results. The result of the comparison is a pass/fail designation. In addition, the comparison of the expected test results with the actual test results provides information on the exact location of the failure. Also, since the test pattern generation and comparison circuit architecture is compatible with hardware description languages such as Verilog HDL or VHDL, the test pattern generation and comparison circuit can be automatically generated with a silicon compiler.

Claims68

Dependent claims

A test pattern generation and comparison apparatus in communication with a built-in-self-test controller and functional integrated circuits, comprising:

a background and command decoder connected to receive test background and command codes from said test controller, to translate said test background and command codes to multiple bit test stimulus signals that, when applied to said functional integrated circuits, create test response signals from said functional integrated circuits;
and
a plurality of latency buffers connected to said background and command decoder to receive said multiple bit test stimulus signals and to adjust in time the relationship of the bits of said multiple bit test stimulus signals as required by said functional integrated circuits.

A built-in-self test circuit incorporated with functional integrated circuits on a semiconductor substrate to verify correctness of operation of said functional integrated circuits, comprising:

a built-in-self-test controller to provide test background and command codes indicating tests to be performed on said functional integrated circuits;
and
a test pattern generation and comparison apparatus in communication with the built-in-self-test controller to receive said test background and command codes and with said functional integrated circuits to transmit at least one test stimulus signal to said integrated circuit and to receive at least one test response signal to evaluate correctness of operation of said integrated circuit, comprising:
a background and command decoder connected to receive said test background and command codes from said test controller, to translate said test background and command codes to multiple bit test stimulus signals that, when applied to said functional integrated circuits, create said test response signals from said functional integrated circuits;
and
a plurality of latency buffers connected to said background and command decoder to receive said multiple bit test stimulus signals and to adjust in time the relationship of the bits of said multiple bit test stimulus signals as required by said functional integrated circuits.

3 more elements

A computer implemented hardware design system having a code retention device retaining a hardware description coding of a test pattern generation and comparison circuit, which, when executed, automatically creates a physical description of said hardware description coding during an automatic physical design of an integrated circuit for placement on a semiconductor substrate, said hardware description coding comprising:

a descriptive coding of a background and command decoder connected to receive test background and command codes from said test controller, to translate said test background and command codes to multiple bit test stimulus signals that, when applied to said functional integrated circuits, create test response signals from said functional integrated circuits;
and
a descriptive coding of a plurality of latency buffers connected to said background and command decoder to receive said multiple bit test stimulus signals and to adjust in time the relationship of each bit of said multiple bit test stimulus signals as required by said functional integrated circuits.

A data retention medium readable by a computer system containing a hardware description coding of a test pattern generation and comparison circuit, which, when exectuted, automatically creates a physical description of said hardware description coding during an automatic physical design of an integrated circuit for placement on a semiconductor substrate, said hardware description coding comprising:

a descriptive coding of a background and command decoder connected to receive test background and command codes from said test controller, to translate said test background and command codes to multiple bit test stimulus signals that, when applied to said functional integrated circuits, create test response signals from said functional integrated circuits;
and
a descriptive coding of a plurality of latency buffers connected to said background and command decoder to receive said multiple bit test stimulus signals and to adjust in time the relationship of said multiple bit test stimulus signals as required by said functional integrated circuits.

A method for generation of test patterns to be communicated to integrated circuits and comparison of test response patterns communicated from said integrated circuit to verify function of said integrated circuits, comprising the steps of:

receiving a test pattern command indicating which tests to be performed are communicated to said integrated circuit;
receiving a background pattern code indicating a pattern of multiple bit test stimulus signals to be communicated to said integrated circuit;
decoding said test pattern command and said background pattern code to create said multiple bit test stimulus signals;
adjusting a timing relation of said multiple bit test stimulus signals to provide correct timing relationships for said multiple bit test stimulus signals;
and
communicating said multiple bit test stimulus signals to said integrated circuit.

3 more elements

Dependencies are inferred from the claim text.

Test pattern generator for SRAM and DRAM

Life of this patent

Test pattern generator for SRAM and DRAM

Life of this patent

Abstract

Claims68