Nonvolatile data storage circuit using ferroelectric capacitors

A nonvolatile data storage circuit, comprising:

• a data latch circuit having first and second storage nodes;
• first and second ferroelectric capacitors one electrode of which is connected to said first storage node, and third and fourth ferroelectric capacitors one electrode of which is connected to said second storage node;
• wherein
• during a store operation to write data of said data latch circuit to said ferroelectric capacitors, a first plate signal is supplied to the other electrodes of said first and third ferroelectric capacitors, a second plate signal is supplied to the other electrodes of said second and fourth ferroelectric capacitors, and the timing of either the rising or the falling, or both, of said first and second plate signals are made different.

A nonvolatile data storage circuit, comprising:

• a data holding circuit having a storage node;
• and
• a pair of ferroelectric capacitors one electrode of each of which is connected to said storage node;
• wherein
• during a recall operation to rewrite data from said ferroelectric capacitors to said data holding circuit, the timing of first and second plate signals supplied to the other electrodes of said pair of ferroelectric capacitors is shifted, when said first plate signal is applied said data holding circuit is activated to latch the data, and thereafter said second plate signal is applied.

A nonvolatile memory circuit, comprising:

• a plurality of word lines;
• a plurality of bit line pairs;
• and
• a plurality of memory cells placed at positions of intersection of said word lines and said bit line pairs;
• wherein
• each of said memory cells has a data latch circuit having first and second storage nodes, first and second ferroelectric capacitors one electrode of each of which is connected to said first storage node, and third and fourth ferroelectric capacitors one electrode of each of which is connected to said second storage node;
• and,
• during a store operation to write data from said data latch circuit to said ferroelectric capacitors, a first plate signal is supplied to the other electrodes of said first and third ferroelectric capacitors, a second plate signal is supplied to the other electrodes of said second and fourth ferroelectric capacitors, and timing of either rising or falling, or both, of said first and second plate signals is different.