Method, apparatus and computer program product for efficient, large counts of per thread performance events

An apparatus for counting performance events for a computing system, wherein the system includes i) a processor having a set of on-chip performance monitoring counter registers and ii) system memory, wherein the apparatus includes instructions with which the processor is operable to perform the steps of:

• a) designating a first one of the counters as a low-order counter for counting a certain performance event encountered by the processor;
• b) associating with the first counter a second one of the counters as a high-order counter for the performance event;
• c) incrementing the first counter responsive to detecting the performance event for a first processing thread;
• d) updating, responsive to a second thread becoming active, an accumulator in system memory for the first thread and first and second counters;
• e) loading, responsive to the first thread becoming active, values of the first and second counters from the accumulator, so that while the first thread is active the values of the first and second counters provide a consistent meaning relative to values that were read during a previous time when the first thread was active, despite any intervening thread switches;
• and
• f) performing, responsive to a user call to read and return a combined value from the first and second counters, an operation comprising the steps of:
• reading a first instance of the second counter;
• reading the first counter;
• and
• reading a second instance of the second counter before returning the combined value.

A computer program product for counting performance events for a computing system, wherein the system includes i) a processor having a set of on-chip performance monitoring counter registers and ii) system memory, the computer program product comprising:

• instructions for designating a first one of the counters as a low-order counter for counting a certain performance event encountered by the processor;
• instructions for associating with the first counter a second one of the counters as a high-order counter for the performance event;
• instructions for incrementing the first counter responsive to detecting the performance event for a first processing thread;
• instructions for updating, responsive to a second thread becoming active, an accumulator in system memory for the first thread and first and second counters;
• instructions for loading, responsive to the first thread becoming active, values of the first and second counters from the accumulator, so that while the first thread is active the values of the first and second counters provide a consistent meaning relative to values that were read during a previous time when the first thread was active, despite any intervening thread switches;
• and
• instructions for performing, responsive to a user call to read and return a combined value from the first and second counters, a certain operation comprising the steps of:
• reading a first instance of the second counter;
• reading the first counter;
• and
• reading a second instance of the second counter before returning the combined value.