Algorithms tunning for dynamic lot dispatching in wafer and chip probing

A method for dynamic adjustment of priority and step procedures for determining effective lot dispatching for wafer and chip probing, comprising:

• A. using a two-phased, event-driven dispatching system structure for said dynamic adjustment;
• B. using said step procedures to choose lots that can utilize incorporated auxiliary apparatus without need for new setup;
• C. providing for engineering lots capacity check in said step procedures;
• D. solving dispatching conflict between wafer and package lots, and
• E. limiting tester's capability in product through use of common constraint system,
• wherein a multi-priority factor and multi-dispatching step procedure is enhanced to fit complex dispatching demands of a test foundry and used with chip probing and final testing.

A method for dynamic adjustment of priority and step procedures for determining effective lot dispatching for wafer and chip probing, comprising:

• A. using a two-phased, event-driven dispatching system structure for said dynamic adjustment;
• B. using said step procedures to choose lots that can utilize incorporated auxiliary apparatus without need for new setup;
• C. providing for engineering lots capacity check in said step procedures;
• D. solving dispatching conflict between wafer and package lots, and
• E. limiting tester's capability in product through use of common constraint system,
• wherein said method is based on distinct production goals or behavior reported by production and engineering devices to in real time get the most desirable dispatching list for a particular tester at any given time.

A method for dynamic adjustment of priority and step procedures for determining effective lot dispatching for wafer and chip probing, comprising:

• A. using a two-phased, event-driven dispatching system structure for said dynamic adjustment;
• B. using said step procedures to choose lots that can utilize incorporated auxiliary apparatus without need for new setup;
• C. providing for engineering lots capacity check in said step procedures;
• D. solving dispatching conflict between wafer and package lots, and
• E. limiting tester's capability in product through use of common constraint system,
• wherein said engineering lot capacity limitation check is done to see if the amount of fixed testing time per week determined by testing site personnel for engineering lots to be tested on any particular machine has been exceeded.

A method for dynamic adjustment of priority and step procedures for determining effective lot dispatching for wafer and chip probing, comprising:

• A. using a two-phased, event-driven dispatching system structure for said dynamic adjustment;
• B. using said step procedures to choose lots that can utilize incorporated auxiliary apparatus without need for new setup;
• C. providing for engineering lots capacity check in said step procedures;
• D. solving dispatching conflict between wafer and package lots, and
• E. limiting tester's capability in product through use of common constraint system,
• wherein said common constraint system is a PROMIS constraint system, and
• wherein said PROMIS constraint system provides a function for users to limit said tester's product capability from which said step procedure's last step is to check said PROMIS constraint system to filter out inappropriate lots to avoid mistake operations.

A system for dynamic adjustment of priority and step procedures for determining effective lot dispatching for wafer and chip probing, comprising:

• a means to use a two-phased, event-driven dispatching system structure for said dynamic adjustment, wherein said two-phased, event-driven dispatching system structure comprises lot rank and lot assignment, said lot rank comprises of a lot rank priority formula for production wafers and packages and a lot rank for engineering lots, and wherein said priority formula of:
• Priority=Σ(Base*Weightx) calculates priority;
• a means to use said step procedures to choose lots that can utilize incorporated auxiliary apparatus without need for new setup;
• a means to provide engineering lots capacity check in said step procedures;
• a means to solve dispatching conflict between wafer and package lots, and
• means to limit tester's capability in product through constraint.

A system for dynamic adjustment of priority and step procedures for determining effective lot dispatching for wafer and chip probing, comprising:

• a means to use a two-phased, event-driven dispatching system structure for said dynamic adjustment,
• a means to use said step procedures to choose lots that can utilize incorporated auxiliary apparatus without need for new setup;
• a means to provide engineering lots capacity check in said step procedures;
• a means to solve dispatching conflict between wafer and package lots, and
• means to limit tester's capability in product through constraint, wherein a multi-priority factor and multi-dispatching step procedure is enhanced to fit complex dispatching demands of a test foundry and used with chip probing and final testing.

A system for dynamic adjustment of priority and step procedures for determining effective lot dispatching for wafer and chip probing, comprising:

• a means to use a two-phased, event-driven dispatching system structure for said dynamic adjustment,
• a means to use said step procedures to choose lots that can utilize incorporated auxiliary apparatus without need for new setup;
• a means to provide engineering lots capacity check in said step procedures;
• a means to solve dispatching conflict between wafer and package lots, and
• means to limit tester's capability in product through constraint,
• wherein based on distinct production goals or behavior reported by production and engineering devices to in real time get the most desirable dispatching list for a particular tester at any given time.

A system for dynamic adjustment of priority and step procedures for determining effective lot dispatching for wafer and chin probing, comprising:

• a means to use a two-phased, event-driven dispatching system structure for said dynamic adjustment,
• a means to use said step procedures to choose lots that can utilize incorporated auxiliary apparatus without need for new setup;
• a means to provide engineering lots capacity check in said step procedures;
• a means to solve dispatching conflict between wafer and package lots, and
• means to limit tester's capability in product through constraint,
• wherein said engineering lot capacity limitation check is done to see if the amount of fixed testing time per week determined by testing site personnel for engineering lots to be tested on any particular machine has been exceeded.