Shared memory architecture in GPS signal processing
AssigneeSiRF Technology, Inc.
InventorsLeon Kuo-Liang Peng, Henry D. Falk
Life of this patent
Estimating the term…
Abstract
A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.
Claims13
A shared memory architecture for a receiver system comprising a memory space shared commonly by two or more receiver functions, the memory space including space occupied by a first memory and a second memory, wherein the first memory accumulates coherent integration results and the second memory accumulates non-coherent integration results, and wherein the receiver functions comprises a correlator signal processing, a tracking processing and an application processing unit.
A method for sharing memory among receiver functions, said method comprising:
- providing a memory space occupied by a first memory and a second memory, wherein the first memory accumulates coherent integration results and the second memory accumulates non-coherent integration results;
- allocating the memory space using a first set of address ranges for receiver functions operable during a first signal acquisition mode of a receiver;
- and
- using a second set of address ranges for receiver functions operable during a second signal acquisition mode of the receiver.
Dependencies are inferred from the claim text.