US 6,930,324 B2 · Device architecture and process for improved vertical memory arrays

Abstract

An array process diagnosis test structure for an integrated circuit including a transistor array composed of vertical FET memory cell access transistors, which are formed into the depth of a substrate in the form of active webs which run parallel in the lateral direction of the circuit is disclosed. Memory cell storage capacitors in the array test structure are formed in deep trenches on the end faces of those sections of the active webs which form the vertical FET transistors. Word lines are arranged along the webs and along parallel intersecting bit lines of the array, outside of which, and on two mutually opposite edges, are located a first and second word line comb. The wordline combs are offset and connected alternately to different word lines. In addition, a first and a second bit line comb are formed on the two other opposing edges of the transistor array mutually offset and each connected to different bit lines. The test structure provides a convenient means to carry out reliability investigations on the gate oxide of the vertical FET transistors and on the capacitor dielectric in the deep trenches, capacitance measurements between the word lines, and between the word lines and other circuit layers, as well as capacitance measurements between the bit lines and between the bit lines and other circuit layers, and thus facilitates diagnosis of possible fault sources arising during the production process.

Claims19

Dependent claims

An integrated circuit comprising:

a vertical FET access transistor array formed into the depth of a substrate in active webs which run parallel in the lateral direction of the integrated circuit and are implemented as vertical trenches;
an array of storage capacitors, wherein each storage capacitor is associated with a vertical FET access transistor and is formed in a deep trench on a face of a section of an active web which forms the vertical FET access transistor;
a series of wordlines arranged along the active webs;
a series of bitlines intersecting the wordlines;
and
an array process diagnosis test structure, wherein the process diagnosis test structure is connected to the wordlines and wherein the connection to the wordlines forms a wordline comb structure, wherein the comb structure comprises:
a first wordline comb connected by a series of contacts to a first series of non-adjacent wordlines along a first edge of the transistor array, wherein the spacing between each successive wordline in the first series of non-adjacent wordlines is defined by a parameter n;
and
a second wordline comb connected by a series of contacts to a second series of non-adjacent wordlines along a second edge of the transistor array opposite to the first edge, wherein the spacing between each successive wordline in the second series of non-adjacent wordlines is defined by the parameter n, and wherein the first series and second series of wordlines are offset such that no wordlines are common to both the first and second series.

6 more elements

An integrated circuit comprising:

a vertical FET access transistor array formed into the depth of a substrate in active webs which run parallel in the lateral direction of the integrated circuit and are implemented as vertical trenches;
an array of storage capacitors, wherein each storage capacitor is associated with a vertical FET access transistor and is formed in a deep trench on a face of a section of an active web which forms the vertical FET access transistor;
a series of wordlines arranged along the active webs;
a series of bitlines intersecting the wordlines;
an array process diagnosis test structure, wherein the process diagnosis test structure is connected to the wordlines and wherein the connection to the wordlines farms a wordline comb structure, wherein the process diagnosis test structure is connected to the bitlines and wherein the connection to the bitlines forms a bitline comb structure;
and
a buried drain contact strip formed in a desired region of the transistor array and arranged parallel to the direction of the bit lines, wherein the buried drain contact strip is formed where the layout areas of a deep trench and an active web intersect;
whereby the buried contact strip establishes a contact between a storage capacitor formed in a deep trench, and an associated vertical FET transistor, and whereby contact between semiconductor memory cells in the desired region and an associated bit line is made.

5 more elements

Dependencies are inferred from the claim text.

Device architecture and process for improved vertical memory arrays

Life of this patent

Device architecture and process for improved vertical memory arrays

Life of this patent

Abstract

Claims19