Synchronous signal producing circuit for controlling a data ready signal indicative of end of access to a shared memory and thereby controlling synchronization between processor and coprocessor
AssigneeRenesas Technology Corp.
InventorAkira Yamada
Life of this patent
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Abstract
A synchronous signal producing circuit includes an access inhibit region register for designating an access inhibit region for a processor in a shared memory, a comparing circuit for detecting the access by the processor to the access inhibit region designated in the access inhibit region register, and a logic circuit for issuing a P_DC signal setting the processor to a wait state based on a coprocessor instruction execution signal and a result of the comparison by the comparing circuit.
Claims20
A synchronous signal producing circuit for synchronizing access by a processor and a coprocessor to a shared memory, comprising:
- an access inhibit region register for designating an access inhibit region for said processor in said shared memory;
- a comparing circuit for detecting the access by said processor to said access inhibit region designated in said access inhibit region register;
- and
- a first logic circuit for issuing a signal setting said processor to a wait state based on a signal indicating that said coprocessor is executing a coprocessor instruction as well as a result of the comparison by said comparing circuit, and maintaining said signal setting said processor to the wait state until said processor completes to execute the coprocessor instruction.
A processor system comprising:
- a processor;
- a coprocessor;
- a shared memory connected to said processor and said coprocessor;
- and
- a synchronous signal producing circuit for synchronizing access by said processor and said coprocessor to said shared memory, wherein
- said synchronous signal producing circuit includes:
- an access inhibit region register for designating an access inhibit region for said processor in said shared memory;
- a comparing circuit for detecting the access by said processor to said access inhibit region designated in said access inhibit region register;
- and
- a first logic circuit for issuing a signal setting said processor to a wait state based on a signal indicating that said coprocessor is executing a coprocessor instruction as well as a result of the comparison by said comparing circuit, and maintaining said signal setting said processor to the wait state until said coprocessor completes to execute the coprocessor instruction.
A method of producing a synchronous signal for synchronizing access by a processor and a coprocessor to a shared memory, comprising the steps of:
- designating an access inhibit region for said processor in said shared memory;
- detecting the access by said processor to said designated access inhibit region;
- and
- producing a signal setting said processor to a wait state based on a signal indicating that said coprocessor is executing a coprocessor instruction as well as a result of said detection, and maintaining said signal setting said processor to the wait state until said coprocessor completes to execute the coprocessor instruction.
Dependencies are inferred from the claim text.