US 6,928,128 B1Granted

Clock alignment circuit having a self regulating voltage supply

AssigneeRambus Inc.

InventorStefanos Sidiropoulos

Life of this patent

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Abstract

Clock alignment circuits and techniques for reducing power dissipation, increasing power supply noise immunity, decreasing process and temperature variation sensitivity, and providing a wide operating range. A power supply generator generates an isolated supply voltage for a delay line used in a clock alignment circuit. The delay line generates a delayed clock from a reference clock. A comparator detects a correction information (i.e., delay or phase error) between the delayed clock and the reference clock and generates error information representative of the correction information. A charge pump circuit converts the error information into a voltage signal, wherein the voltage signal is a scaled representation of the error information. The power supply generator includes an amplifier having a first input coupled to the voltage signal and an output to provide the supply voltage and a capacitor coupled between the supply voltage and a ground voltage, wherein the amplifier tracks the voltage signal level to regulate the supply voltage.

Claims21

Dependent claims

A clock alignment circuit comprising:

delay line having a plurality of delay elements, wherein each delay element of the plurality of delay elements includes a supply electrode to receive a supply voltage, to generate a delayed clock signal with respect to a reference clock signal;
a comparator, coupled to the delay line, to compare the delayed clock signal and the reference clock signal and to output delay differential information, wherein the delay differential information is representative of a correction information between the reference clock signal and the delayed clock signal;
charge pump circuitry, coupled to the comparator, to convert the delay differential information to a control signal, wherein the control signal is proportional to the delay differential information;
an amplifier coupled to the charge pump circuitry, wherein the amplifier includes:
a first input to receive the control signal;
a second input to receive a feedback signal;
and
an output to provide the supply voltage and the feedback signal;
a capacitor coupled between the supply voltage and a secondary power supply,
wherein the amplifier further includes:
a current mirror load having a first and a second load transistor coupled in parallel, the first and the second load transistors each having a supply electrode coupled to a first supply voltage;
a bias transistor coupled to a second supply voltage, the bias transistor responding to a bias voltage to provide a bias current at a drain electrode;
a first differential input transistor having a source coupled to the drain electrode of the bias transistor, wherein the first differential input transistor is coupled in series with the first load transistor;
and
a second differential input transistor having a source coupled to the drain electrode of the bias transistor, wherein the second differential input transistor is coupled in series with the second load transistor.

12 more elements

A clock alignment circuit comprising:

a delay line having a plurality of delay elements, wherein each delay element of the plurality of delay elements includes a supply electrode to receive a supply voltage, to generate a delayed clock signal with respect to a reference clock signal;
a comparator, coupled to the delay line, to compare the delayed clock signal and the reference clock signal and to output delay differential information, wherein the delay differential information is representative of a correction information between the reference clock signal and the delayed clock signal;
charge pump circuitry, coupled to the comparator, to convert the delay differential information to a control signal, wherein the control signal is proportional to the delay differential information;
an amplifier coupled to the charge pump circuitry, wherein the amplifier includes:
a first input to receive the control signal;
a second input to receive a feedback signal;
and
an output to provide the supply voltage and the feedback signal;
a capacitor coupled between the supply voltage and a secondary power supply,
wherein the charge pump circuitry includes:
a first current source to receive a first supply voltage, the first current source having a control electrode to receive a bias control signal;
a first load transistor coupled to a first reference terminal;
a first input transistor coupled in series between the first current source and the first load transistor, the first input transistor responds to a first phase input to provide a first pump output;
a second current source receiving a second supply voltage, the second current source having a control electrode to receive the bias control signal;
a second load transistor coupled to a second reference terminal, wherein the second load transistor responds to the first pump output;
a second input transistor coupled in series between the second current source and the second load transistor, the second input transistor responsive to a second phase input to provide a charge pump output;
and
a current source control coupled between a third supply voltage and a third reference terminal, the current source control includes a control input transistor responsive to the charge pump output and a current source control to provide the bias control signal, wherein the bias control signal is responsive to the charge pump output;
and
a capacitor coupled between the charge pump output and a fourth reference terminal, wherein the charge pump output provides the control signal.

17 more elements

A power supply generator for generating a first supply voltage for clock alignment circuitry wherein the clock alignment circuitry includes a delay line having a plurality of delay elements, each delay element of the plurality of delay elements includes a source electrode to receive the first supply voltage, the delay line generating a delayed clock using a reference clock, the clock alignment circuitry further including a comparator to detect a correction information between the delayed clock and the reference clock to generate error information representative of the correction information, and a charge pump to convert the error information into a control signal, wherein the control signal is proportional to the error information, the power supply generator comprising:

an operational amplifier having an output to provide the first supply voltage, wherein the operational amplifier includes:
a bias transistor biased by a bias voltage;
a differential amplifier coupled to the bias transistor, wherein the differential amplifier includes a first differential input to receive the control signal and a second differential input coupled to the output in an inverting configuration;
a bias generator to provide the bias voltage, the bias generator having a first input coupled to the control signal and a second input to receive the bias voltage;
wherein, in response to the control signal, the bias generator provides the bias voltage representative of a change in the control signal;
and
a capacitor coupled between the output and a supply terminal.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/303,669Filed 3 May 1999
Granted: 9 Aug 2005
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H03L 7/0812
Provided with an additional controlled phase shifter: and where no voltage or current controlled oscillator is used
H03K 5/133
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: using a chain of active delay…
H03L 7/0896
Details of the current generators: the current generators being controlled by differential up-down pulses
H03K 2005/00026
Variable delay: controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter