US 6,927,463 B2 · Semiconductor device and method for fabricating the same

Abstract

A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the plurality of shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to a corresponding one of the shallow well regions, and the shallow well region is electrically separated from the adjacent shallow well region.

Claims45

Dependent claims

A semiconductor device comprising:

a semiconductor substrate;
a deep well region of a first conductivity type, formed in the semiconductor substrate;
one or more shallow well regions of a second conductivity type, formed in the deep well region;
a source region and a drain region of the first conductivity type formed in each of the one or more shallow well regions;
corresponding to each shallow well region,
a channel region, formed between the source region and the drain region of that shallow well region;
a gate insulating film formed on the channel region of that shallow well region;
and
a gate electrode formed on the gate insulating film of that shallow well region,
wherein each of the one or more shallow well regions is electrically separated from adjacent ones of the one or more adjacent shallow well regions by a groove type element separation structure,
corresponding to each groove type element separation structure, an impurity diffusion region, having a same conductivity type as the deep well region, is provided on a bottom of that groove type element separation structure and reaches the deep well region, and
for each shallow well region, a difference of a potential formed between that shallow well region and the source region for that shallow well region and a difference of a potential formed between that shallow well region and the drain region for that shallow well region is set so as to be smaller than a built-in potential of a pn junction formed between that shallow well region and the source region for that shallow well region and the built-in potential of a pn junction formed between that shallow well region and the drain region for that shallow well region, respectively, during operation.

9 more elements

A semiconductor device comprising:

a semiconductor substrate;
a deep well region of a first conductivity type, formed in the semiconductor substrate;
a groove type element separation structure formed in the deep well region;
one or more shallow well regions of a second conductivity type, each shallow well region formed in one or more island active regions surrounded by the groove type element separation structure;
for each shallow well region,
a source region and a drain region of the first conductivity type and a contact region formed in the one or more island active regions in which that shallow well region is formed;
a channel region formed between the source region and the drain region and adjacent to the contact region;
a gate insulating film formed on the channel region;
a gate electrode formed from above the gate insulating film to above the contact region,
wherein the gate electrode is electrically connected to that shallow well region at the contact regions;
and
wherein a high concentration impurity diffusion region is formed in the contact regions;
wherein the deep well region of the first conductivity type is capable of functioning as an emitter or a collector of a bipolar transistor;
each of the one or more shallow well regions of the second conductivity type are capable of functioning as a base of the bipolar transistor;
for each of the one or more shallow well regions, the source region and the drain region of the first conductivity type are capable of functioning as the collector or the emitter of the bipolar transistor;
wherein the semiconductor device is operated by a combination of an operation of a MOS transistor and an operation of the bipolar transistor.

13 more elements

A semiconductor device comprising:

a semiconductor substrate;
active regions formed on the semiconductor substrate;
a deep well region, of a first conductivity type, formed in the semiconductor substrate;
one or more shallow well regions, of a second conductivity type, formed in the deep well region;
for each shallow well region,
a source region and a drain region, of the first conductivity type, formed therein;
a channel region formed between the source region and the drain region;
a gate insulating film formed on the channel region;
a gate electrode formed on the gate insulating film;
a groove type first element separation region which electrically separates that shallow well regions from adjacent ones of the shallow well regions;
and
a second element separation region, which is thicker than the gate insulating film, formed between the groove type first element separation regions.

9 more elements

A semiconductor device comprising:

a semiconductor substrate;
a deep well region of a first conductivity type, formed in the semiconductor substrate;
one or more shallow well regions, of a second conductivity type, formed in the deep well region;
for each shallow well region,
a source region and a drain region, of the first conductivity type, formed therein;
a channel region formed between the source region and the drain region;
a gate insulating film formed on the channel region;
a contact region formed adjacent to the channel region and in the shallow well region, and
a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to the shallow well region, and
each shallow wall region is electrically separated from adjacent ones of the shallow well regions,
wherein, for each shallow well region,
the gate electrode includes a polycrystalline silicon film formed on the gate insulating film and a metal silicide film formed on the polycrystalline silicon film, and
the metal silicide film is electrically connected to that shallow well region via the contact region of that shallow well region.

10 more elements

A semiconductor device comprising:

a semiconductor substrate;
a deep well region of a first conductivity type, formed in the semiconductor substrate;
one or more shallow well regions of a second conductivity type, formed in the deep well region;
for each shallow well region,
a source region and a drain region of the first conductivity type, formed therein;
a channel region formed between the source region and the drain region;
a gate insulating film formed on the channel region;
a contact region formed adjacent to the channel region and in the shallow well region, and
a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to the shallow well region,
each shallow well region is electrically separated from adjacent ones of the shallow well regions,
the semiconductor device further comprising an interlayer insulating film and an upper wiring provided on the interlayer insulating film,
wherein, for each shallow well region
a contact hole is formed in the interlayer insulating film, which penetrates through the gate electrode of that shallow well region and the gate insulating film of that shallow well region so as to reach the contact region of that shallow well region,
an electrical connection is formed between the upper wiring and that shallow well region on the bottom of the contact hole for that shallow well region, and
an electrical connection is formed between the gate electrode of that shallow well region and the upper wiring on at least a side wall region of the contact hole for that shallow well region.

12 more elements

A semiconductor device comprising a first block circuit and a second block circuit, wherein:

the first block circuit is positioned between a power supply voltage source and a circuit block constituted by using a semiconductor device comprising:
a semiconductor substrate;
an n-type deep well region formed in the semiconductor substrate;
a p-type deep well region formed in the semiconductor substrate;
one or more p-type shallow well regions formed in the n-type deep well region;
one or more n-type shallow well regions formed in the p-type deep well region;
an N-channel MOS transistor formed in each of the one or more p-type shallow well regions;
and
a P-channel MOS transistor formed in each of the one or more n-type shallow well regions,
wherein,
for each p-type shallow well region,
the N-channel MOS transistor includes an n-type source region and an n-type drain region formed therein, a channel region formed between the n-type source region and the n-type drain region, a contact region formed adjacent to the channel region and in the p-type shallow well region,
a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film, and
the gate electrode of the N-channel MOS transistor is electrically connected to that p-type shallow well region,
for each n-type shallow well region,
the P-channel MOS transistor includes a p-type source region and a p-type drain region formed therein, a channel region formed between the p-type source region and the p-type drain region, a contact region formed adjacent to the channel region and in the n-type shallow well region, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film, and
the gate electrode of the P-channel MOS transistor is electrically connected to that n-type shallow well region;
the second block circuit is positioned between the circuit block and a ground voltage supply source, and
supply of a power supply voltage or supply of a ground voltage or both of the supply of the power supply voltage and the supply of the ground voltage are blocked when the circuit block is in a standby state.

16 more elements

A method for operating a semiconductor device comprising the steps of:

providing an operating state of a semiconductor device comprising:
a semiconductor substrate;
an n-type deep well region formed in the semiconductor substrate;
a p-type deep well region formed in the semiconductor substrate;
one or more p-type shallow well regions formed in the n-type deep well region;
one or more n-type shallow well regions formed in the p-type deep well region;
for each p-type shallow well region, an N-channel MOS transistor formed therein;
and
for each n-type shallow well region, a P-channel MOS transistor formed therein,
wherein each N-channel MOS transistor includes
an n-type source region and an n-type drain region formed in p-type shallow well regions in which that N-channel MOS transistor is formed,
a channel region formed between the n-type source region and the n-type drain region,
a contact region formed adjacent to the channel region and in the p-type shallow region, and
a gate insulating film formed on the channel region, and
a gate electrode formed on the gate insulating film and electrically connected to the p-type shallow well region;
and
wherein each P-channel MOS transistor includes
a p-type source region and a p-type drain region formed in the n-type shallow well region in which that p-channel MOS transistor is formed
a channel region formed between the p-type source region and the p-type drain region,
a contact region formed adjacent to the channel region and in the n-type shallow well region,
a gate insulating film formed on the channel region, and
a gate electrode formed on the gate insulating film and electrically connected to the n-type shallow well region;
for each p-channel MOS transistor,
obtaining a difference of a maximum potential formed between the p-type source and drain regions and the n-type shallow well region in which the p-channel MOS transistor is formed, and
maintaining said maximum potential difference so as to be smaller than a built-in potential formed between the p-type source and drain regions and the n-type shallow well region in which the p-channel MOS transistor is formed;
and
for each n-channel MOS transistor,
obtaining a difference of a maximum potential formed between the n-type source and drain regions and the p-type shallow well region in which the n-channel MOS transistor is formed;
and
maintaining said maximum potential difference so as to be smaller than a built-in potential formed between the n-type source and drain regions and the p-type shallow well region in which the n-channel MOS transistor is formed.

27 more elements

A semiconductor device comprising:

a semiconductor substrate;
an n type deep well region formed in the semiconductor substrate;
a p type deep well region formed in the semiconductor substrate;
one or more p type shallow well regions formed in the n type deep well region;
one or more n type shallow well regions formed in the p type deep well region;
an N channel MOS transistor respectively formed in the one or more p type shallow well regions;
and
a P channel MOS transistor respectively formed in the one or more n type shallow well regions,
wherein the N channel MOS transistor includes an n type source region and an n type drain region formed in a corresponding one of the one or more p type shallow well regions, a channel region formed between the n type source region and the n type drain region a contact region formed adjacent to the channel region and in the p-type shallow region, a gate insulating film formed pn the channel region, and a gate electrode formed on the gate insulating film,
wherein the P channel MOS transistor includes a p type source region and a p type drain region formed in a corresponding one of the one or more n type shallow well regions, a channel region formed between the p type source region and the p-type drain region, a contact region formed adjacent to the channel region and in the n-type shallow well region, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film,
wherein the gate electrode of the N channel MOS transistor is electrically connected to the p type shallow well region, and the gate electrode of the P channel MOS transistor is electrically connected to the n type shallow well region, and
wherein a difference of a potential formed between a corresponding one of the one or more n type or p type shallow well regions and the source region and a difference of a potential formed between a corresponding one of the one or more n type or p type shallow well regions and the drain region are set so as to be smaller than a built in potential of a pn junction formed between the source/drain regions and the corresponding one of the one or more n type or p type shallow well regions of a different conductivity type from the source/drain regions during operation.

9 more elements

Dependencies are inferred from the claim text.

Semiconductor device and method for fabricating the same

Life of this patent

Semiconductor device and method for fabricating the same

Life of this patent

Abstract

Claims45