Shared bit line cross-point memory array incorporating P/N junctions
AssigneeSharp Laboratories of America, Inc.
InventorSheng Teng Hsu
Life of this patent
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Abstract
A shared bit line cross-point memory array structure is provided, along with methods of manufacture. The memory structure comprises a bottom word line with a top word line overlying the bottom word line. A bit line is interposed between the bottom word line and the top word line such that a first cross-point is formed between the bottom word line and the bit line and a second cross-point is formed between the bit line and the top word line. A resistive memory material is provided at each cross-point above and below the bit line. A diode is formed at each cross-point between the resistive memory material and either the top word line or the bottom word line, respectively.
Claims13
A memory structure comprising:
- a) a substrate;
- b) a plurality of doped lines overlying the substrate and isolated from each other by shallow trench isolation;
- c) a plurality of bit electrodes overlying the doped bit lines at an angle, whereby a cross-point is formed at each location where a bit electrode crosses a doped bit line;
- d) a plurality of diodes comprising the doped lines and a doped region of opposite polarity in contact with the doped lines, with each doped region located at a cross-point;
- e) a plurality of bottom electrodes overlying the plurality of diodes;
- f) a resistive memory active layer interposed between the plurality of bit electrodes and the plurality of bottom electrodes;
- g) a second resistive memory active layer overlying the plurality of bit electrodes;
- h) a plurality of stacked electrodes overlying the second resistive memory active layer;
- and
- i) a plurality of top electrodes overlying the stacked electrodes to form a cross-point array with the plurality of bit electrodes.
Dependencies are inferred from the claim text.