Methods of fabricating multiple sets of field effect transistors
AssigneeMicron Technology, Inc.
InventorsFred D. Fishburn, Martin Ceredig Roberts
Life of this patent
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Abstract
The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.
Claims21
A method of fabricating multiple sets of field effect transistors, comprising:
- forming an etch stop layer over an insulative capping layer over a conductive gate layer over a substrate, the etch stop layer and the insulative capping layer being of different compositions;
- patterning and etching the etch stop layer, the insulative capping layer, and the conductive gate layer to form a first set of conductive gate constructions over the substrate;
- forming and planarizing a dielectric material over the first set of gate constructions;
- after forming and planarizing the dielectric material, patterning and etching the insulative capping layer and the conductive gate layer to form a second set of conductive gate constructions over the substrate;
- and
- wherein the patterning and etching the insulative capping layer and the conductive gate layer to form the second set of conductive gate constructions also patterns and etches remnant of the etch stop layer to constitute a portion of the second set of conductive gate constructions.
A method of fabricating multiple sets of field effect transistors, comprising:
- forming an etch stop layer over an insulative capping layer over a conductive gate layer over a substrate, the etch stop layer being formed to a first thickness;
- patterning and etching the etch stop layer, the insulative capping layer, and the conductive gate layer to form a first set of conductive gate constructions over the substrate;
- forming and anisotropically etching an insulative spacer forming layer over the first set of conductive gate constructions effective to form insulative spacers, the etch stop layer restricting etching of the insulative capping layer during the anisotropically etching;
- after forming the insulative spacers, forming and planarizing a dielectric material over the first set of gate constructions, and effective to remove all remaining of the etch stop layer from the substrate during said planarizing;
- after forming and planarizing the dielectric material, forming a mass of material over the substrate to a second thickness which is within ten percent of the first thickness;
- and
- after forming and planarizing the dielectric material, patterning and etching the mass of material, the insulative capping layer and the conductive gate layer to form a second set of conductive gate constructions over the substrate.
Dependencies are inferred from the claim text.