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AssigneeSanDisk Corporation
InventorsEliyahou Harari, George Samachisa, Jack H. Yuan, Daniel C. Guterman
Estimating the term…
Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.
In an array of non-volatile memory cells including source and drain regions spaced apart in a first direction across a surface of a semiconductor substrate and connected to bit lines extending in a second direction, the first and second directions being orthogonal with each other, a method of storing charge in a plurality of neighboring regions of a charge-trapping dielectric on the substrate surface positioned at least over substrate channel regions between source and drain regions of individual memory cells, comprising:
In a non-volatile memory cell array, a method of storing levels of charge representing data in a plurality of neighboring regions of charge-trapping dielectric sandwiched between at least one conductive control gate and a surface of a semiconductor substrate between source and drain regions of individual memory cells, comprising storing charge in a first of said plurality of dielectric regions by source side injection and storing charge in a second of said plurality of dielectric regions by hot-electron injection.
In a non-volatile memory cell array, a method of storing levels of charge representing data in a plurality of neighboring regions of charge-trapping dielectric on a surface of a semiconductor substrate between source and drain regions thereof, comprising storing charge in first and second of said plurality of neighboring regions by at least two different mechanisms selected from a group consisting of source side injection, hot-electron injection, Fowler-Nordheim tunneling and ballistic injection.
In a non-volatile memory cell array, a method of storing levels of charge representing data in a plurality of neighboring non-overlapping regions of charge-trapping dielectric sandwiched between at least one conductive control gate and a surface of a semiconductor substrate within individual memory cells, comprising storing a first charge level in a first of said plurality of dielectric regions by source side injection and storing a second charge level in a second of said plurality of dielectric regions by hot-electron injection, the method resulting in their respective first and second stored charge levels existing at the same time.
A method of storing data in charge-trapping dielectric material of individual memory cells of an array formed on a semiconductor substrate, comprising:
Dependencies are inferred from the claim text.