Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics

A method of forming a transistor comprising:

• forming first and second source/drain regions in a substrate;
• forming a body region between the first and second source/drain regions;
• forming a dielectric film on the body region between the first and second source/drain regions;
• and
• coupling a gate to the dielectric film, wherein forming the dielectric film on the body region includes:
• forming a layer of hafnium oxide on a substrate in a reaction chamber by atomic layer deposition using a HfI4 precursor;
• and
• forming a layer of zirconium oxide on the layer of hafnium oxide to form a HfO2/ZrO2 composite, wherein the HfO2/ZrO2 composite is a nanolaminate having a final layer of hafnium oxide and an initial layer of hafnium oxide on the substrate.

A method of forming a memory array comprising:

• forming a number of access transistors, at least one of the access transistors including a dielectric film containing a HfO2/ZrO2 nanolaminate on a body region between a first and second source/drain regions, the HfO2/ZrO2 nanolaminate having a final layer of hafnium oxide and an initial layer of hafnium oxide on the body region, the dielectric film containing a HfO2/ZrO2 nanolaminate formed by a method including:
• forming a layer of hafnium oxide on a substrate in a reaction chamber by atomic layer deposition using a HfI4 precursor;
• and
• forming a layer of zirconium oxide on the layer of hafnium oxide;
• forming a number of word lines coupled to a number of the gates of the number of access transistors;
• forming a number of source lines coupled to a number of the first source/drain regions of the number of access transistors;
• and
• forming a number of bit lines coupled to a number of the second source/drain regions of the number of access transistors.

A method of forming an electronic system comprising:

• providing a processor;
• coupling a memory array to the processor, wherein the memory array includes at least one access transistor having a dielectric film containing a HfO2/ZrO2 nanolaminate on a body region between a first and second source/drain regions, the HfO2/ZrO2 nanolaminate having a final layer of hafnium oxide and an initial layer of hafnium oxide on the body region, the dielectric film containing a HfO2/ZrO2 nanolaminate formed by a method including:
• forming a layer of hafnium oxide on a substrate in a reaction chamber by atomic layer deposition using a HfI4 precursor;
• and
• forming a layer of zirconium oxide on the layer of hafnium oxide;
• and
• forming a system bus that couples the processor to the memory array.