Timing calibration apparatus and method for a memory device signaling system

A memory system, comprising:

• a memory controller;
• a memory component having a memory core for holding read data information and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;
• the interface of the memory component configured to:
• receive a timing signal;
• receive a first signal with read request information;
• retrieve the read data information from the memory core in response to the request information;
• and
• transmit a second signal containing the read data information, wherein the read data information is comprised of read data symbols and where the average duration of the read data symbols, measured at the interface, defines a symbol time interval, wherein the read request information includes a first read request and a second read request having an internal access time similar to an internal read access time of the first read request;
• wherein operation of the memory component is characterized by:
• a first external access time interval, measured at the interface, between a timing event on the timing signal that is associated with the first read request and respective first read data transmitted by the interface in response to the first read request;
• a second external access time interval, measured at the interface, between a timing event on the timing signal that is associated with the second read request and respective second read data transmitted by the interface in response to the second read request;
• and
• the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

A memory system, comprising:

• a memory controller;
• a memory component having a memory core for holding read data information and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;
• the interface of the memory component configured to:
• receive a first signal with timing information;
• retrieve the read data information from the memory core;
• and
• transmit a second signal containing the read data information, wherein the read data information is comprised of read data symbols and where the average duration of the read data symbols, measured at the interface, defines a symbol time interval;
• wherein operation of the memory component is characterized by:
• a first drive offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first read data symbol transmitted by the interface, the first timing event associated with the first read data symbol;
• a second drive offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second read data symbol transmitted by the interface, the second timing event associated with the second read data symbol;
• and
• the difference between the first drive offset time and the second drive offset time is greater than one-half of the symbol time interval.

A system, comprising:

• a first component;
• a second component, the second component including storage for holding data information and an interface that is coupled to at least one bus that is also coupled to the first component for conveying signals between the first component and the second component;
• the interface of the second component configured to:
• receive a timing signal;
• retrieve the data information from the storage;
• and
• transmit a second signal containing the data information, wherein the data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval;
• wherein operation of the second component is characterized by:
• a first drive offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first data symbol transmitted by the interface, the first timing event associated with the first data symbol;
• a second drive offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second read data symbol transmitted by the interface, the second timing event associated with the second data symbol;
• and
• the difference between the first drive offset time and the second drive offset time is greater than one-half of the symbol time interval.

A device comprising a single integrated circuit having a plurality of internal modules, the device comprising:

• a first module;
• and
• a second module having storage for holding data information and an interface that is coupled to at least one bus that is also coupled to the first module for conveying signals between the first module and the second module;
• the interface of the second module configured to:
• receive a first signal with timing information;
• retrieve the data information from the storage;
• and
• transmit a second signal containing the data information, wherein the data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval;
• wherein operation of the component is characterized by:
• a first drive offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first data symbol transmitted by the interface, the first timing event associated with the first data symbol;
• a second drive offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second data symbol transmitted by the interface, the second timing event associated with the second data symbol;
• and
• the difference between the first drive offset time and the second drive offset time is greater than one-half of the symbol time interval.

A memory component comprising:

• a memory core for holding read data information;
• and
• an interface configured to:
• receive a first signal with read request information;
• retrieve the read data information from the memory core in response to the request information;
• and
• transmit a second signal containing the read data information, wherein the read data information is comprised of read data symbols and where the average duration of the read data symbols, measured at the interface, defines a symbol time interval, wherein the read request information includes a first read request and a second read request having an internal access time similar to an internal read access time of the first read request;
• wherein operation of the memory component is characterized by:
• a first external access time interval, measured at the interface, between the first read request and respective first read data transmitted by the interface in response to the first read request;
• a second external access time interval, measured at the interface, between the second read request and respective second read data transmitted by the interface in response to the second read request;
• and
• the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

A memory component comprising:

• a memory core for holding read data information;
• and
• an interface configured to:
• receive a timing signal;
• receive a first signal with read request information;
• retrieve the read data information from the memory core in response to the request information;
• and
• transmit a second signal containing the read data information, wherein the read data information is comprised of read data symbols and where the average duration of the read data symbols, measured at the interface, defines a symbol time interval, wherein the read request information includes a first read request and a second read request having an internal access time similar to an internal read access time of the first read request;
• wherein operation of the memory component is characterized by:
• a first external access time interval, measured at the interface, between a timing event on the timing signal that is associated with the first read request and respective first read data transmitted by the interface in response to the first read request;
• a second external access time interval, measured at the interface, between a timing event on the timing signal that is associated with the second read request and respective second read data transmitted by the interface in response to the second read request;
• and
• the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

A memory component comprising:

• a memory core for holding read data information;
• and
• an interface configured to:
• receive a timing signal;
• retrieve the read data information from the memory core;
• and
• transmit a second signal containing the read data information, wherein the read data information is comprised of read data symbols and where the average duration of the read data symbols, measured at the interface, defines a symbol time interval;
• wherein operation of the memory component is characterized by:
• a first drive offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first read data symbol transmitted by the interface, the first timing event associated with the first read data symbol;
• a second drive offset time interval, measured at the interface, between a second timing event on the timing signal and respective second read data symbol transmitted by the interface, the second timing event associated with the second read data symbol;
• and
• the difference between the first drive offset time and the second drive offset time is greater than one-half of the symbol time interval.

A device comprising a single integrated circuit having a plurality of modules, the device comprising:

• a non-memory module;
• storage for holding data information;
• and
• an interface configured to:
• receive a timing signal;
• retrieve the data information from the storage;
• and
• transmit a second signal containing the data information, wherein the data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval;
• wherein operation of the electronic device is characterized by:
• a first drive offset time interval, measured at the interface, between a first timing event on the timing signal and respective first data symbol transmitted by the interface, the first timing event associated with the first data symbol;
• a second drive offset time interval, measured at the interface, between a second timing event on the timing signal and respective second read data symbol transmitted by the interface, the second timing event associated with the second data symbol;
• and
• the difference between the first drive offset time and the second drive offset time is greater than one-quarter of the symbol time interval.

A memory system, comprising:

• a memory controller;
• a memory component having a memory core for holding data and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;
• the interface of the memory component configured to:
• receive a timing signal;
• receive a first signal from the memory controller with write request information;
• receive a second signal from the memory controller with write data information;
• store the write data information in the memory core in response to the write request information;
• and
• wherein the write data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval, wherein the write request information includes a first write request and a second write request having an internal access time similar to an internal write access time of the first write request;
• wherein operation of the memory component is characterized by:
• a first external access time interval, measured at the interface of the memory component, between the first write request and a respective first write data symbol received by the memory component in conjunction with the first write request;
• a second external access time interval, measured at the interface of the memory component, between the second write request and a respective second write data symbol received by the memory component in conjunction with the second write request;
• and
• the difference between the first external access time interval and the second external access time interval is greater than one-half of the symbol time interval.

A memory system, comprising:

• a memory controller;
• a memory component having a memory core for holding data and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;
• the interface of the memory component configured to:
• receive a first signal from the memory controller with write request information;
• receive a second signal from the memory controller with write data information;
• store the write data information in the memory core in response to the write request information;
• and
• wherein the write data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval, wherein the write request information includes a first write request and a second write request having an internal access time similar to an internal write access time of the first write request;
• wherein operation of the memory component is characterized by:
• a first external access time interval, measured at the interface of the memory component, between a first timing event on the timing signal and a respective first write data symbol received by the memory component in conjunction with the first write request, the first timing event associated with the first write request;
• a second external access time interval, measured at the interface of the memory component, between a second timing event on the timing signal and a respective second write data symbol received by the memory component in conjunction with the second write request, the second timing event associated with the second write request;
• and
• the difference between the first external access time interval and the second external access time interval is greater than one-half of the symbol time interval.

A memory system, comprising:

• a memory controller;
• a memory component having a memory core for holding data and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;
• the interface of the memory component configured to:
• receive a timing signal;
• receive a first signal from the memory controller with write request information;
• receive a second signal from the memory controller with write data information;
• store the write data information in the memory core in response to the write request information;
• and
• wherein the write data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval, wherein the write request information includes a first write request and a second write request having an internal access time similar to an internal write access time of the first write request;
• wherein operation of the memory component is characterized by:
• a first offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first write data symbol received by the interface, the first timing event associated with the first write data symbol;
• a second offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second write data symbol received by the interface, the second timing event associated with the second write data symbol;
• and
• the difference between the first offset time and the second offset time is greater than one-half of the symbol time interval.

A system, comprising:

• a first component;
• a second component, the second component including storage for holding data and an interface that is coupled to at least one bus that is also coupled to the first component for conveying signals between the first component and the second component;
• the interface of the second component configured to:
• receive a timing signal;
• receive a second signal from the first component with write data information;
• store the write data information in the storage;
• and
• wherein the write data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval;
• wherein operation of the second component is characterized by:
• a first offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first write data symbol received by the interface, the first timing event associated with the first write data symbol;
• a second offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second write data symbol received by the interface, the second timing event associated with the second write data symbol;
• and
• the difference between the first offset time and the second offset time is greater than one-half of the symbol time interval.

A device comprising a single integrated circuit having a plurality of modules, the device comprising:

• a first module comprising a controller;
• and
• a second module having a memory core for holding data and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;
• the interface of the second module configured to:
• receive a timing signal;
• receive a first signal from the controller with write request information;
• receive a second signal from the controller with write data information;
• store the write data information in the memory core in response to the write request information;
• and
• wherein the write data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval, wherein the write request information includes a first write request and a second write request having an internal access time similar to an internal write access time of the first write request;
• wherein operation of the memory component is characterized by:
• a first offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first write data symbol received by the interface, the first timing event associated with the first write data symbol;
• a second offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second write data symbol received by the interface, the second timing event associated with the second write data symbol;
• and
• the difference between the first offset time and the second offset time is greater than one-half of the symbol time interval.

A memory component comprising:

• a memory core for holding data;
• an interface configured to:
• receive a first signal with write request information;
• receive a second signal with write data information;
• store the write data information in the memory core in response to the write request information;
• and
• wherein the write data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval, wherein the write request information includes a first write request and a second write request having an internal access time similar to an internal write access time of the first write request;
• wherein operation of the memory component is characterized by:
• a first external access time interval, measured at the interface of the memory component, between the first write request and a respective first write data symbol received by the memory component in conjunction with the first write request;
• a second external access time interval, measured at the interface of the memory component, between the second write request and a respective first write data symbol received by the memory component in conjunction with the second write request;
• and
• the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

A memory component comprising:

• a memory core for holding data;
• an interface configured to:
• receive a timing signal;
• receive a first signal with write request information;
• receive a second signal with write data information;
• store the write data information in the memory core in response to the write request information;
• and
• wherein the write data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval, wherein the write request information includes a first write request and a second write request having an internal access time similar to an internal write access time of the first write request;
• wherein operation of the memory component is characterized by:
• a first external access time interval, measured at the interface of the memory component, between a first timing event on the timing signal and a respective first write data symbol received by the memory component in conjunction with the first write request, the first timing event associated with the first write request;
• a second external access time interval, measured at the interface of the memory component, between a second timing event on the timing signal and a respective second write data symbol received by the memory component in conjunction with the second write request, the second timing event associated with the second write request;
• and
• the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

A memory component, comprising:

• a memory core for holding data and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;
• the interface of the memory component configured to:
• receive a timing signal;
• receive a second signal with write data information to be stored in the memory core;
• and
• store the write data information in the memory core;
• wherein the write data information is comprised of write data symbols and where the average duration of the write data symbols, measured at the interface, defines a symbol time interval;
• wherein operation of the memory component is characterized by:
• a first offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first write data symbol received by the interface, the first timing event associated with the first write data symbol;
• a second offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second write data symbol received by the interface, the second timing event associated with the second write data symbol;
• and
• the difference between the first offset time and the second offset time is greater than one-half of the symbol time interval.

A device comprising a single integrated circuit having a plurality of modules, the device comprising:

• storage for holding data;
• an interface coupled to the storage, the interface configured to:
• receive a timing signal;
• receive a second signal with write data information;
• and
• store the write data information in the storage;
• wherein the write data information is comprised of write data symbols and where the average duration of the write data symbols, measured at the interface, defines a symbol time interval;
• wherein operation of the second component is characterized by:
• a first offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first write data symbol received by the interface, the first timing event associated with the first write data symbol;
• a second offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second write data symbol received by the interface, the second timing event associated with the second write data symbol;
• and
• the difference between the first offset time and the second offset time is greater than one-half of the symbol time interval.

A memory system, comprising:

• a memory controller;
• a first memory component having an interface coupled to the memory controller, the interface configured to receive respective read data symbols from the first memory component, where average duration of the respective read data symbols, measured at the interface of the first memory component, defines a symbol time interval;
• the interface of the first memory component also configured to receive from the memory controller respective request signals, including a first read request;
• and
• a second memory component having an interface coupled to the memory controller, the interface configured to receive second read data symbols from the second memory component;
• the interface of the second memory component also configured to receive from the memory controller respective request signals, including a second read request;
• a first external access time interval, measured at the interface of the first memory component, between the first read request and a respective first read data symbol retrieved by the first memory component in response to the first read request;
• a second external access time interval, measured at the interface of the second memory component, between the second read request and a respective second read data symbol retrieved by the second memory component in response to the second read request;
• and
• wherein the first and second memory components are coupled to the memory controller by different data buses and by a common request bus that conveys the respective request signals, and the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

A memory system, comprising:

• a memory controller;
• a first memory component having an interface coupled to the memory controller, the interface configured to receive respective read data symbols from the first memory component, where average duration of the respective read data symbols, measured at the interface of the first memory component, defines a symbol time interval;
• the interface of the first memory component also configured to receive from the memory controller a timing signal and respective request signals, the request signals including a first read request;
• and
• a second memory component having an interface coupled to the memory controller, the interface configured to receive second read data symbols from the second memory component;
• the interface of the second memory component also configured to receive from the memory controller the timing signal and respective request signals, including a second read request;
• a first external access time interval, measured at the interface of the first memory component, between a first timing event on the timing signal and a respective first read data symbol retrieved by the first memory component in response to the first read request, the first timing event associated with the first read request;
• a second external access time interval, measured at the interface of the second memory component, between the first timing event on the timing signal and a respective second read data symbol retrieved by the second memory component in response to the first read request, the second timing event associated with the first read request;
• and
• wherein the first and second memory components are coupled to the memory controller by different data buses and by a common request bus that conveys the respective request signals, and the difference between the first external access time interval and the second external access time interval is greater than one-half of the symbol time interval.

A memory system, comprising:

• a memory controller;
• a first memory component having an interface coupled to the memory controller, the interface configured to receive respective write data symbols from the memory controller, where average duration of the respective write data symbols, measured at the interface of the first memory component, defines a symbol time interval;
• the interface of the first memory component also configured to receive from the memory controller respective write request signals, including a first write request;
• and
• a second memory component having an interface that is coupled to the memory controller, the interface of the second memory component configured to receive respective write data symbols from the memory controller;
• the interface of the second memory component also configured to receive from the memory controller respective write request signals, including a second write request;
• and
• a first external access time, measured at the interface of the first memory component, between the first write request and a respective first write data symbol received by the first memory component in conjunction with the first write request;
• a second external access time, measured at the interface of the second memory component, between the first write request and a respective second write data symbol retrieved by the second memory component in response to the first write request;
• and
• the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

A memory system, comprising:

• a memory controller;
• a first memory component having an interface coupled to the memory controller, the interface configured to receive respective write data symbols from the memory controller, where average duration of the respective write data symbols, measured at the interface of the first memory component, defines a symbol time interval;
• the interface of the first memory component also configured to receive from the memory controller respective timing signal and write request signals, including a first write request;
• and
• a second memory component having an interface that is coupled to the memory controller, the interface of the second memory component configured to receive respective write data symbols from the memory controller;
• the interface of the second memory component also configured to receive from the memory controller the timing signals and respective write request signals, including a second write request;
• and
• a first external access time, measured at the interface of the first memory component, between a first timing event on the timing signal and a respective first write data symbol received by the first memory component in conjunction with the first write request, the first timing event associated with the first write request;
• a second external access time, measured at the interface of the second memory component, between the first timing event on the timing signal and a respective second write data symbol retrieved by the second memory component in response to the second write request;
• and
• the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

A memory system, comprising:

• a memory controller having an interface that is coupled to a first data bus and a second data bus;
• and
• a memory component having an interface that is coupled to the first data bus and the second data bus;
• the system having a first mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the second data bus;
• and
• the system having a second mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the first data bus.

A memory controller comprising:

• an interface that is coupled to a first data bus and a second data bus;
• and
• logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the second data bus;
• and
• the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the first data bus.

A memory component comprising,

• a memory core for holding read data information;
• an interface that is coupled to a first data bus and a second data bus;
• and
• logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location in the memory core to be transferred on the first data bus and causes a second data symbol associated with a second memory location in the memory core to be transferred on the second data bus;
• and
• the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the first data bus.

A memory system, comprising:

• a memory controller having an interface that is coupled to a first data bus and a second data bus;
• and
• a memory component having an interface that is coupled to the first data bus and the second data bus;
• the system having a first mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the second data bus;
• and
• the system having a second mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and causes the second data symbol associated with the second memory location to be transferred on the first data bus after the first data symbol has been transferred on the first data bus.

A memory controller comprising:

• an interface that is coupled to a first data bus and a second data bus;
• and
• logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the second data bus;
• and
• the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and causes the second data symbol associated with the second memory location to be transferred on the first data bus after the first data symbol has been transferred on the first data bus.

A memory component comprising,

• a memory core for holding read data information;
• an interface that is coupled to a first data bus and a second data bus;
• and
• logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location in the memory core to be transferred on the first data bus and causes a second data symbol associated with a second memory location in the memory core to be transferred on the second data bus;
• and
• the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and causes the second data symbol associated with the second memory location to be transferred on the first data bus after the first data symbol has been transferred on the first data bus.

A memory system, comprising:

• a memory controller having an interface that is coupled to a first data bus;
• and
• a memory component having an interface that is coupled to the first data bus;
• the system having a first mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the first data bus after the first data symbol has been transferred;
• and
• the system having a second mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the first data bus.

A memory controller comprising:

• an interface that is coupled to a first data bus;
• and
• logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the first data bus after the first data symbol has been transferred;
• and
• the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the first data bus.

A memory component comprising,

• a memory core for holding read data information;
• an interface that is coupled to a first data bus;
• and
• logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the first data bus after the first data symbol has been transferred;
• and
• the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the first data bus.

A memory system, comprising:

• a memory controller having an interface that is coupled to a first data bus and a second data bus;
• and
• a memory module having an interface that is coupled to the first data bus and the second data bus;
• the system having a first mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the second data bus;
• and
• the system having a second mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the second data bus.

A memory controller comprising:

• an interface that is coupled to a first data bus and a second data bus;
• and
• logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the second data bus;
• and
• the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the second data bus.

A memory component comprising,

• a memory core for holding read data information;
• an interface that is coupled to a first data bus and a second data bus;
• and
• logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the second data bus;
• and
• the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the second data bus.