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US 6,917,661 B1Granted
Method, architecture and circuitry for controlling pulse width in a phase and/or frequency detector
AssigneeCypress Semiconductor Corporation
InventorsPaul H. Scott, S. Babar Raza
Life of this patent
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Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a parallel output data signal in response to (i) a first clock signal and (ii) one or more serial data signals. The second circuit may be configured to present the one or more serial data signals and the first clock signal in response to (i) a second clock signal and (ii) a parallel input data signal.
Claims19
An apparatus comprising:
- a first circuit configured to present a parallel output data signal in response to (i) a selected phase of a plurality of phases of a first multi-phased clock signal and (ii) two or more serial data signals;
- and
- a second circuit configured to present said two or more serial data signals and said first clock signal in response to (i) a second clock signal and (ii) a parallel input data signal.
A circuit comprising:
- means for generating a parallel output data signal in response to (i) a selected phase a plurality of phases of a multi-phased first clock signal and (ii) two or more serial data signals;
- and
- means for generating said two or more serial data signals and said multi-phased first clock signal in response to (i) a second clock signal and (ii) a parallel input data signal.
A method for controlling a pulse width in a phase and/or frequency detector comprising the steps of:
- (A) generating a parallel output data signal in response to (i) a selected phase of a plurality of phases of a multi-phased first clock signal and (ii) two or more serial data signals;
- and
- (B) generating said two or more serial data signals and said first clock signal in response to (i) a second clock signal and (ii) a parallel input data signal, wherein said multi-phased first clock signal is configured to control said pulse width.
An apparatus comprising:
- a first circuit configured to present a parallel output data signal in response to (i) a selected phase of a first clock signal and (ii) two or more serial data signals;
- a second circuit configured to present said two or more serial data signals and said first clock signal in response to (i) a second clock signal and (ii) a parallel input data signal;
- and
- a third circuit configured to generate (i) one or more select signals and (ii) a selected clock signal in response to (i) said first clock signal and (ii) a phase select signal.
1 more element
Dependencies are inferred from the claim text.