Erasing storage nodes in a bi-directional nonvolatile memory cell
AssigneeMulti Level Memory Technology
InventorSau Ching Wong
Life of this patent
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Abstract
A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. An erase operation can use a negative voltage on the control and a positive voltage on an underlying well or source/drain region to cause tunneling that discharges one or both floating gates. Applying a limited current to a source/drain region during an erase operation can cause the source/drain region and a floating gate to rise together and avoid band-to-band tunneling and resulting hole injection into the floating gate.
Claims16
An erase operation for a memory transistor including a substrate having a first source/drain region, a second source/drain region, and a channel extending between the first and second source/drain region, a first floating gate overlying and insulated from a first end regions of the channel, a second floating gate overlying and insulated from a second end regions of the channel, and a control gate overlying and insulated from the first and second floating gates and a central portion of the channel, the erase operation comprising:
- biasing the control gate at a negative voltage;
- biasing a well in the substrate to a positive voltage wherein a voltage difference between the control gate and the well is sufficient to induce charge tunneling between the first and second floating gates and the well;
- and
- applying the biasing of the control gate and the well to remove any excess electrons from the first and second floating gates.
An erase operation for a memory transistor including a substrate having a first source/drain region, a second source/drain region, and a channel extending between the first and second source/drain region, a first floating gate overlying and insulated from a first end regions of the channel, a second floating gate overlying and insulated from a second end regions of the channel, and a control gate overlying and insulated from the first and second floating gates and a central portion of the channel, the erase operation comprising:
- biasing the control gate at a negative voltage;
- and
- biasing the first source/drain region to a positive voltage wherein a voltage difference between the control gate and the first source/drain region is sufficient to induce charge tunneling between the first source/drain region and the first floating gate.
An erase operation for a memory transistor comprising:
- biasing a control gate of the memory transistor at a negative voltage;
- and
- applying limited current to a source/drain region of the memory transistor so that voltages on the source/drain region and a floating gate of the memory transistor rise together and avoid band-to-band tunneling and resulting hole injection into the floating gate, the source/drain region reaching a positive voltage wherein a voltage difference between the control gate and the source/drain region is sufficient to induce charge tunneling between the source/drain region and the floating gate.
Dependencies are inferred from the claim text.