US 6,914,547 B1Granted

Triple resistor string DAC architecture

AssigneeAnalog Devices, Inc.

InventorsPrem S Swaroop, Arindam Raychaudhuri, Kaushal Kumar Jha

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Abstract

A technique to provide a higher resolution DAC architecture for converting an N-bit digital word to a corresponding analog voltage signal without increasing chip area and switching capacitance. In one example embodiment, this is accomplished by using a triple string converter. In the triple string converter, a triple switching tree is coupled to a triple resistor string and to an analog output. Each switching tree includes a plurality of switches and each resistor string includes a plurality of corresponding resistors. A logic decoder coupled to the triple switching tree receives an N-bit digital word and generates a digital signal. The plurality of switches in each switching tree is substantially simultaneously controlled by the digital signal to output a range of corresponding analog voltage signals when the triple resistor string is connected across a voltage supply.

Claims22

Dependent claims

A digital-to-analog converter, comprising:

a triple switching tree switchably coupled to a triple resistor string and to an analog output,
wherein the triple resistor string includes a first resistor string having a first plurality of resistors for coupling across the voltage supply, a second resistor string having a second plurality of resistors, and a third resistor string having a third plurality of resistors, and
wherein the triple switching tree comprises a first switching network comprising a first mirror-imaged plurality of switches, wherein each of the first mirror-imaged plurality of switches having an input connected to one of the first plurality of resistors and an output to couple across the second resistor string;
a second switching network comprising a second mirror-imaged plurality of switches, wherein each of the second mirror-imaged plurality of switches having an input connected to one of the second plurality of resistors and an output to couple across the third resistor string;
and
a third switching network comprising a third mirror-imaged plurality of switches, wherein each of the mirror-imaged plurality of switches having an input connect to one of the third plurality of resistors and an output to connect to the analog output,
wherein the plurality of switches in each branch is substantially simultaneously controlled by an N-bit digital word to output a range of corresponding analog voltage signals, and wherein the triple switching tree is operable when the triple resistor string is coupled across a voltage supply.

4 more elements

A digital-to-analog converter circuit, comprising:

a first resistor string having a first plurality of resistors to couple across a voltage supply;
a second resistor string having a second plurality of resistors;
a third resistor string having a third plurality of resistors;
a first switching network comprising a first mirror-imaged plurality of switches, wherein each of the first mirror-imaged plurality of switches having an input connected to one of the first plurality of resistors and an output to couple across the second resistor string;
a second switching network comprising a second mirror-imaged plurality of switches, wherein each of the second mirror-imaged plurality of switches having an input connected to one of the second plurality of resistors and an output to couple across the third resistor string;
and
a third switching network comprising a third mirror-imaged plurality of switches, wherein each of the mirror-imaged plurality of switches having an input connect to one of the third plurality of resistors and an output to connect to a common output.

4 more elements

A digital-to-analog converter for converting a digital word into a corresponding analog signal, comprising:

a first resistor string having a first plurality of resistors to couple across a voltage supply;
a second resistor string having a pair of terminals, wherein the second resistor string includes a second plurality of resistors;
a third resistor string having a pair of terminals, wherein the third resistor string includes a third plurality of resistors;
a first switching network comprising a first mirror-imaged plurality of switches to couple to a voltage produced across a selected one of the first plurality of resistors via the first mirror-imaged plurality of switches coupled to the associated first plurality of resistors, wherein the first switching network is coupled to the pair of terminals in the second resistor string, wherein the second plurality of resistors produces voltages in response to a current passing via the first resistor string to the second resistor string via the first switching network;
a second switching network comprising a second mirror-imaged plurality of switches to couple to a voltage produced across a selected one of the second plurality of resistors via the second mirror-imaged plurality of switches coupled to the associated second plurality of resistors, wherein the second switching network is coupled to the pair of terminals in the third resistor string, wherein the third plurality of resistors produces voltages in response to a current passing via the second resistor string to the third resistor string via the second switching network;
and
a third switching network comprising a third mirror-imaged plurality of switches, wherein each of the third mirror-imaged plurality of switches having an input connected to one of the third plurality of resistors and an output to connect to a common output, wherein the third switching network to couple to one of the voltages produced by a selected one of the third plurality of resistors to the common output.

4 more elements

A digital-to-analog converter with cascaded coarse and fine resistor divider strings, comprising:

a primary resistor string having a first plurality of resistors to couple across a voltage supply;
a secondary resistor string having a pair of terminals, wherein the secondary resistor string includes a second plurality of resistors;
a tertiary resistor string having a pair of terminals, wherein the tertiary resistor string includes a third plurality of resistors;
a primary switching network comprising a plurality of switches to couple to a voltage produced across a selected one of the first plurality of resistors in response to a first set of logic signals via the first plurality of switches coupled to the associated first plurality of resistors, wherein the primary switching network is coupled to the pair of terminals in the secondary resistor string, wherein the second plurality of resistors produces voltages in response to a current passing via the primary resistor string to the secondary resistor string via the primary switching network;
a secondary switching network comprising a plurality of switches to couple to a voltage produced across a selected one of the second plurality of resistors in response to a second set of logic signals via the second plurality of switches coupled to the associated second plurality of resistors, wherein the secondary switching network is coupled to the pair of terminals in the tertiary resistor string, wherein the third plurality of resistors produces voltages in response to a current passing via the secondary resistor string to the tertiary resistor string via the secondary switching network;
and
a tertiary switching network comprising a plurality of switches, wherein each of the third plurality of switches having an input connected to one of the third plurality of resistors and an output to connect to a common output, wherein the tertiary switching network to couple to one of the voltages produced by a selected one of the tertiary plurality of resistors to the common output in response to a third set of logic signals.

4 more elements

An integrated circuit, comprising:

a first resistor string having a first plurality of resistors to couple across a voltage supply;
a second resistor string having a second plurality of resistors;
a third resistor string having a third plurality of resistors;
a first switching network comprising a first mirror-imaged plurality of switches, wherein each of the first mirror-imaged plurality of switches having an input connected to one of the first plurality of resistors and an output to couple across the second resistor string;
a second switching network comprising a second mirror-imaged plurality of switches, wherein each of the second mirror-imaged plurality of switches having an input connected to one of the second plurality of resistors and an output to couple across the third resistor string;
a third switching network comprising a third mirror-imaged plurality of switches, wherein each of the mirror-imaged plurality of switches having an input connect to one of the third plurality of resistors and an output to connect to a common output;
and
a logic decoder to couple to the first, second, and third switching networks, wherein the logic decoder receives a digital input and outputs first, second, and third sets of logic signals as a function of the digital input, and wherein the first, second, and third switching networks receive the first, second, and third sets of logic signals and selects one of the first, second, and third plurality of resistors via the first, second, and third mirror-imaged plurality of switches coupled to the associated first, second, and third plurality of resistors, respectively.

5 more elements

Dependencies are inferred from the claim text.