Method and apparatus for suppressing low frequency content in digital data
AssigneeSeagate Technology LLC
InventorsBane Vasic, Erozan M. Kurtas
Life of this patent
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Abstract
A method of encoding digital information in order to suppress dc includes the steps of receiving a sequence of m message bits of a message word, and mapping the sequence of m message bits of the message word to a codeword, of length n bits, generated from the m message bits using algebraic operations. Multiple codeword candidates are generated from the m message bits using the algebraic operations to combine the m message bits with different periodic scrambling sequences. One of the codeword candidates is selected for mapping based upon an optimizing criteria. Second order digital sum sequences, corresponding to each of the plurality of codeword candidates, can be used as the optimizing criteria to select the codeword.
Claims16
A method of encoding digital information in order to suppress direct current (dc) content, the method comprising:
- receiving a sequence of m message bits of a message word;
- mapping the sequence of m message bits of the message word to a codeword, of length n bits, generated from the m message bits using algebraic operations, wherein mapping the sequence of m message bits further comprises:
- generating a plurality of codeword candidates, each of length n bits, from the m message bits using algebraic operations by adding a different one of a plurality of periodic scrambling sequences to the m message bits of the message word;
- and
- selecting one of the plurality of codeword candidates based upon an optimizing criteria.
An encoding apparatus which encodes digital information in order to suppress direct current (dc) content, the encoding apparatus comprising:
- an input receiving a sequence of m message bits of a message word;
- a plurality of parallel processing branches each generating a different codeword candidate from the m message bits using algebraic operations, wherein each of the plurality of parallel processing branches comprises scrambling circuitry which receives the m message bits and a scrambling sequence as inputs and provides as an output a codeword candidate, wherein the scrambling sequence used by each processing branch is different than the scrambling sequence used by all of the others of the plurality of parallel processing branches;
- and
- a selector for selecting one of a plurality of codeword candidates, each generated by a different one of the plurality of parallel processing branches, based upon an optimizing criteria.
An apparatus for encoding digital information in order to suppress direct current (dc) content, the apparatus comprising:
- an input which receives a sequence of m message bits of a message word;
- and
- means for mapping the sequence of m message bits of the message word to a codeword, the means for mapping comprising:
- a plurality of parallel processing branches each generating a different codeword candidate from the m message bits using algebraic operations, each of the plurality of parallel processing branches comprises scrambling circuitry which receives the m message bits and a scrambling sequence as inputs and provides as an output a codeword candidate, wherein the scrambling sequence used by each processing branch is different than the scrambling sequence used by all of the other of the plurality of parallel processing branches;
- and
- a selector for selecting one of a plurality of codeword candidates, each generated by a different one of the plurality of parallel processing branches, based upon an optimizing criteria.
Dependencies are inferred from the claim text.