Single transistor ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric

A method for forming a memory device comprising:

• providing a substrate;
• providing a ferroelectric layer overlying said substrate formed at a temperature substantially equal to or greater than 750 C;
• providing an interfacial oxide layer intermediate said substrate and said ferroelectric layer;
• and
• providing a gate electrode overlying the ferroelectric layer, wherein providing said interfacial layer is carried out substantially automatically during formation of said ferroelectric layer and substantially comprises silicon, oxygen end at least one of the elements selected from a group comprising A =Y, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu or Sc having the general formula SixOyAz, where x,y,z are values between about 0.1 and 10.

A method for forming a memory device comprising:

• providing a substrate;
• providing a ferroelectric layer overlying said substrate formed at a temperature substantially equal to or greater than 750 C;
• providing an interfacial oxide layer intermediate said substrate and said ferroelectnc layer;
• and
• providing a gate electrode overlying the ferroelectric layer wherein a ratio of the thickness of said ferroelectric layer to that of said interfacial layer is substantially on the order of 3:1 or less.

A method for forming a memory device comprising:

• providing a substrate;
• providing a ferroelectric layer overlying said substrate formed at a temperature substantially equal to or greater than 750 C;
• providing an interfacial oxide layer intermediate said substrate and said ferroelectric layer;
• and
• providing a gate electrode overlying the ferroelectric layer, wherein providing said ferroelectric layer comprises providing a ferroelectric layer substantially 60 nm thick.

A method for forming a memory device comprising:

• providing a substrate;
• providing a ferroelectric layer overlying said substrate formed at a temperature substantially equal to or greater than 750 C;
• providing an interfacial oxide layer intermediate said substrate and said ferroelectric layer;
• and
• providing a gate electrode overlying the ferroelectric layer, wherein providing said interfacial layer comprises providing an interfacial layer substantially 20 nm thick.