Digital to analog converter with a weighted capacitive circuit

D/A converter including n+1 (n is a natural number) capacitors in total consisting of one terminating capacitor (C0) serving as a unit capacitor and n binary-weighted capacitors (C1-4) that are subjected to binary weighting to the unit capacitor in the ratio of 1:2:4:

• . . . :2(n−1), and, an inverting amplifier (INV1) for obtaining amplified output, the input terminal of the inverting amplifier being connected to first terminal side of the n+1 capacitors in common;
• further comprising:
• a feedback switching means (SWR5) provided between the input and output of the inverting amplifier (INV1) and being in a closed state on reset operation period (T1) and in an open state on output operation period (T2);
• a switching means for terminating operation (SWR0) supplies one of sub reference voltages (VM) obtainable by voltage dividing of two main reference voltages (VB,VT) to second terminal side of the terminating capacitor (C0) on the reset operation period, and then, makes connection of the second terminal side of the terminating capacitor (C0) to the output of the inverting amplifier (INV1) on the output operation period;
• a plurality of switching means for input operation (SWD1-4,SWR1-4) makes selection of one of the two main reference voltages (VB,VT) to be provided for the second terminal side of the n binary-weighted capacitors (C1-4) depending on upper bits of digital data (D1-4) on the reset operation period, and then, makes connection of the second terminal side of the n binary-weighted capacitors (C1-4) to the output of the inverting amplifier (INV1) on the output operation period;
• and,
• sub reference voltage supply means (SUB) for selecting one of m−1 (m is a natural number of 2 or greater) sub reference voltage values obtained by dividing equally into m aliquots between the two main reference voltages (VB,VT) as the sub reference voltage (VM) depending on lower bits of the digital data (D5-8).