Data transmission across asynchronous time domains using phase-shifted data packet

A method of passing data between a first time domain and a second asynchronous time domain, the method comprising:

• receiving a first data signal generated with respect to a reference signal associated with said first time domain, said reference signal having a period of N;
• receiving a second data signal, said second data signal being phase-shifted by a factor of N/2 with respect to said first data signal;
• receiving a third signal, said third data signal being phase-shifted by a factor of N/4 with respect to said reference signal;
• sampling said first data signal, said second data signal and said third signal based at least in part upon a clock signal of said second time domain;
• and selecting between said first and second data signals based at least in part upon said third signal to output valid data independent of said first and second data signal states at the time of sampling.

A method of passing data between a first time domain and a second asynchronous time domain, the method comprising:

• receiving a first data signal generated with respect to a first clock signal associated with said first time domain;
• receiving a second data signal representing said first data signal delayed by a first measure such that during transition of said first data signal said second data signal is valid, and during transition of said second data signal said first data signal is valid;
• receiving a selector signal representing said first clock signal delayed by a second measure;
• and
• selecting between said first and second data signals based at least in part upon a first state of a second clock signal associated with said second time domain and a second state of the selector signal.

A method comprising:

• receiving a first data signal generated with respect to a first clock signal associated with a first time domain;
• generating a second data signal based at least in part upon said first data signal, said second data signal being out of phase with respect to said first data signal by a first measure such that during transition of said first data signal said second data signal is valid, and during transition of said second data signal said first data signal is valid;
• generating a selector signal such that at any given sampling point of said selector signal said selector signal will indicate a valid one of said first and second data signals;
• receiving a second clock signal associated with a second time domain;
• and
• sampling said selector signal said first and second data signals based at least in part upon said second clock signal to output a selected one of said first or second data signals with respect to said second time domain.

An integrated circuit comprising:

• a first delay circuit to generate a selector signal based at least in part upon an input reference signal of a first time domain;
• a second delay circuit to generate a delayed data signal based at least in part upon an input data signal;
• and
• selection logic coupled to the first and second delay circuits to select between said input data signal and said delayed data signal based at least in part upon a state of the selector signal in accordance with an input clock signal of a second time domain, such that at any given sampling point of the input clock signal, the selector signal indicates valid data.

An apparatus comprising:

• first logic to:
• receive a first data signal generated with respect to a first clock signal associated with said first time domain,
• receive a second data signal representing said first data signal delayed by a first measure such that during transition of said first data signal said second data signal is valid, and during transition of said second data signal said first data signal is valid;
• and
• receive a selector signal representing said first clock signal delayed by a second measure such that any given sampling point of said selector signal will indicate valid data, and
• receive a second clock signal associated with said second time domain to sample said first data signal, said second data signal, and said selector signal;
• and
• second logic coupled to said first logic to select between said first and second data signals based at least in part upon a sampled value of said selector signal.