Repairable finite state machines
AssigneeInternational Business Machines Corporation
InventorThomas Schlipf
Life of this patent
Estimating the term…
Abstract
A method and respective hardware logic circuit for implementing partially programmable Finite State Machines in the hardware of digital systems which use finite state machines to implement the control logic of the hardware design. In order to provide a partly reprogrammable Finite State Machine (FSM), which can be reprogrammed in a limited way such that no costly new physical re-build of the chip including said FSM is required, a hardwired FSM includes circuit means that allow that each hardwired product term to be disabled, and further includes means that add programmable product terms which allow adding new behavior to the state machine. Scan-Only SRLs are preferably used to program the required behavior of those programmable product terms.
Claims9
A partly reprogrammable Finite State Machine including a state register holding the current state and two functions (of and nf) comprising combinational logic to calculate the outputs and the next state, respectively, said combinational functions being representable in a “sum of product terms form”, said Finite State Machine comprising:
- a) a circuit disabling a predetermined number of product terms associated with said “sum of product terms form”, each product term corresponding to a given state and a given input vector setting,
- b) a circuit enabling a new product term for a predetermined respective number of new product terms generating for each, a correct output signal corresponding to a given error state and a given error input bit vector, and
- c) said disabling and/or enabling circuits being provided in a form which allows activation thereof in case a product term was tested to include a bug.
Dependencies are inferred from the claim text.