Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics
AssigneeMicron Technology, Inc.
InventorsKie Y. Ahn, Leonard Forbes
Life of this patent
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Abstract
A praseodymium (Pr) gate oxide and method of fabricating same that produces a high-quality and ultra-thin equivalent oxide thickness as compared to conventional SiO2 gate oxides are provided. The Pr gate oxide is thermodynamically stable so that the oxide reacts minimally with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit a Pr layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
Claims55
A method of forming a gate oxide on a transistor body region, comprising:
- evaporation depositing a praseodymium (Pr) layer on the transistor body region;
- and
- oxidizing the Pr layer to form the gate oxide as a Pr2O3 layer on the transistor body region.
A method of forming a gate oxide on a transistor body region, comprising:
- evaporation depositing a praseodymium (Pr) layer on the transistor body region;
- and
- oxidizing the Pr layer using a krypton (Kr)/oxygen (O2) mixed plasma process to form the gate oxide as an oxide layer of Pr2O3 on the transistor body region.
A method of forming a gate oxide on a transistor body region, comprising:
- electron beam evaporation depositing a layer of praseodymium (Pr) on the transistor body region;
- and
- oxidizing the Pr layer to form the gate oxide as a Pr2O3 oxide layer on the transistor body region.
A method of forming a gate oxide on a transistor body region, comprising:
- evaporation depositing a praseodymium (Pr) layer on the transistor body region;
- oxidizing the Pr layer to form the gate oxide as a Pr2O3 layer;
- and
- annealing the Pr2O3 layer.
A method of forming a gate oxide on a transistor body region, comprising:
- evaporation depositing a praseodymium (Pr) layer on the transistor body region;
- and
- oxidizing the Pr layer using a krypton (Kr)/oxygen (O2) mixed plasma process to form the gate oxide as a Pr2O3 layer using an ion bombardment energy less than about 7 eV.
A method of forming a gate oxide on a transistor body region, comprising:
- electron beam evaporation depositing a layer of praseodymium (Pr) on the transistor body region, the body region at a temperature ranging from about 150° C. to about 400° C.;
- oxidizing the Pr layer to form the gate oxide as a Pr2O3 layer.
A method of forming a gate oxide on a transistor body region, comprising:
- electron beam evaporation depositing a layer of praseodymium (Pr) on the transistor body region;
- and
- oxidizing the Pr layer by a krypton(Kr)/oxygen (O2) mixed plasma process using a krypton(Kr)/oxygen (O2) mixed gas that is about 3% oxygen to form the gate oxide as a layer of Pr2O3.
A method of forming a gate oxide on a transistor body region, comprising:
- electron beam evaporation depositing a layer of praseodymium (Pr) on the body region;
- oxidizing the Pr layer by a krypton(Kr)/oxygen (O2) mixed plasma process to form the gate oxide as a layer of Pr2O3;
- and
- conducting the electron beam evaporation and oxidizing the Pr layer at temperatures to inhibit reactions with material forming the body region.
A method of forming a transistor, comprising:
- forming first and second source/drain regions;
- forming a transistor body region between the first and second source/drain regions;
- evaporation depositing a praseodymium (Pr) layer on the transistor body region;
- oxidizing the Pr layer to form a gate oxide as a Pr2O3 layer on the transistor body region;
- and
- coupling a gate to the Pr2O3 layer.
A method of forming a memory array, comprising:
- forming a number of access transistors, comprising:
- forming first and second source/drain regions;
- forming a transistor body region between the first and second source/drain regions;
- evaporation depositing a praseodymium (Pr) layer on the transistor body region;
- oxidizing the Pr layer to form a gate oxide as a Pr2O3 layer on the transistor body region;
- coupling a gate to the Pr2O3 layer;
- forming a number of wordlines coupled to a number of the gates of the number of access transistors;
- forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;
- and
- forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
A method of forming an information handling system, comprising:
- forming a processor;
- forming a memory array, comprising:
- forming a number of access transistors, comprising:
- forming first and second source/drain regions;
- forming a transistor body region between the first and second source/drain regions;
- evaporation depositing a praseodymium (Pr) layer on the transistor body region;
- oxidizing the Pr layer to form a gate oxide as a Pr2O3 layer on the transistor body region;
- coupling a gate to the Pr2O3 layer;
- forming a number of wordlines coupled to a number of the gates of the number of access transistors;
- forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;
- forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors;
- and
- forming a system bus that couples the processor to the memory array.
Dependencies are inferred from the claim text.