Circuit for combining AKB and selective beam current limiting and projection television system utilizing same

A video control circuit for carrying out an automatic kinescope bias control, and an average individual beam current sensing and limiting in respective cathode ray tubes (CRTR, CRTG, CRTB), the video control circuit comprising:

• a video processor (V1);
• and
• a feedback circuit (F) for feeding back proportions of red (R), green (G), and blue (B) cathode currents driving the corresponding cathode ray tubes (CRTR, CRTG, CRTB) to the video processor (V1) for automatic kinescope bias control by adjusting black levels of the respective cathode currents (R, G, B), the feedback circuit (F) comprising at least one average beam current sensing circuit (A) for sensing the proportion of one of the cathode currents (R, G, B), to feed back a beam limiting signal (VABL) to the video processor (V1) for introducing a gain reduction in video gain stages to limit the red (R), green (G) and blue (B) cathode currents in case the proportion of one of the cathode currents (R, G, B) exceeds a predetermined value, wherein the average beam current sensing circuit (A) comprises:
• detection means (R1, C1, Q1) for passing the proportions of red (R), green (G) and blue (B) cathode currents to the video processor (V1) for automatic kinescope bias control in case the proportions of red (R), green (G) and blue (B) cathode currents are below the predetermined value and for detecting the proportions of red (R), green (G) and blue (B) cathode currents in case the proportions of red (R), green (G) and blue (B) cathode currents are above the predetermined value, and
• sensing means (Q2, R5, C2) for sensing portions of the proportions of red (R), green (G) and blue (B) cathode currents exceeding the predetermined value, and wherein the detection means (R1, C1, Q1) comprises a first resistor (R1) and a first transistor (Q1), the first transistor (Q1) having a control terminal coupled to a first reference voltage, a first main terminal coupled to a first terminal of the first resistor (R1), and a second main terminal coupled to the video processor (V1).