Multibit non-volatile memory and method
AssigneesInteruniversitair Microelektronica Centrum (IMEC), Infineon AG
InventorsJan Van Houdt, Luc Haspeslagh
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Abstract
A memory is described having a semiconductor substrate of a first conductivity type, a first and a second junction region of a second conductivity type, whereby said first and said second junction region are part of respectively a first and a second bitline. A select gate is provided which is part of a wordline running perpendicular to said first and said second bitline. Read, write and erase functions for each cell make use of only two polysilicon layers which simplifies manufacture and each memory cell has at least two locations for storing a charge representing at least one bit.
Claims13
A multibit non-volatile memory cell structure comprising:
- a semiconductor substrate of a first conductivity type;
- first and second junction regions of a second conductivity type, said first and said second junction regions defining at least a portion of first and second bitlines, respectively;
- and
- a select gate defining therein at least a portion of a wordline, which extends perpendicular to said first and said second bitlines, wherein read, write and erase functions for each cell involve only two polysilicon layers, and wherein each cell comprises at least two locations for storing a charge representing at least one bit.
A multibit non-volatile memory cell array comprising:
- a plurality of memory cells arranged in an active area region as a matrix of rows and columns, each memory cell comprising:
- a semiconductor substrate of a first conductivity type;
- first and second junction regions of a second conductivity type, said first and said second junction regions forming at least a portion of first and second bitlines, respectively;
- a select gate forming at least a portion of a wordline extending perpendicularly to said first and said second bitlines;
- wherein read, write and erase functions for each cell involve use of only two polysilicon layers, and wherein each memory cell has at least two locations for storing a charge representing at least one bit.
Dependencies are inferred from the claim text.