Methods of forming a transistor having a recessed gate electrode structure
AssigneeAdvanced Micro Devices, Inc.
InventorsChristian Krueger, Thomas Feudel, Volker Grimm
Life of this patent
Estimating the term…
Abstract
In manufacturing a recessed gate transistor, a channel implantation and a source/drain implantation are performed by means of a single implantation mask prior to the formation of a gate opening. Thereafter, the gate opening is formed to a depth that extends substantially to the channel implant so that raised drain and source regions are created which are substantially even with the gate electrode formed in the gate opening. Consequently, expensive and complex epitaxial growth steps can be avoided.
Claims66
A method of forming a recessed gate transistor, the method comprising:
- forming a resist mask over a substrate, said resist mask exposing an active region formed in said substrate;
- implanting a first dopant species of a first conductivity type into said active region to a first depth;
- implanting a second dopant species of an inverse conductivity type relative to said first conductivity type into said active region to a second depth that is less than said first depth;
- and
- forming a gate opening in said active region, wherein a depth of said gate opening substantially corresponds to said second depth.
A method of forming a recessed gate transistor, the method comprising:
- forming a gate opening in an active region formed in a substrate and having a first dopant species of a first conductivity type provided up to a first depth, and a second dopant species of an inverse conductivity type relative to said first conductivity type provided up to a second depth that is less than said first depth, wherein a depth of said gate opening extends substantially to said second depth;
- forming a gate electrode structure in said gate opening;
- and
- annealing said substrate to form source/drain regions and extension regions by diffusing said second dopant species.
A method of forming shallow source/drain extension regions in a recessed gate transistor, the method comprising:
- implanting a first dopant species of a first conductivity type with a first implantation energy into an active region formed in a substrate;
- implanting a second dopant species of an inverse conductive type relative to said first conductivity type with a second implantation energy into said active region;
- forming a recessed gate electrode structure in said active region;
- and
- forming source/drain extension regions adjacent to said gate electrode structure by annealing said substrate.
A method of forming shallow source/drain extension regions in a recessed gate transistor, the method comprising:
- implanting a first dopant species with a first implantation energy into an active region formed in a substrate;
- implanting a second dopant species with a second implantation energy into said active region;
- forming a recessed gate electrode structure in said active region comprising the acts of;
- forming a gate opening in said active region;
- forming dielectric spacer elements on sidewalls of said gate opening;
- forming a gate insulation layer at the bottom of said gate opening;
- filling said gate opening with a gate electrode material;
- removing excess material of said gate electrode material by chemical mechanical polishing;
- and
- forming source/drain extension regions adjacent to said gate electrode structure by annealing said substrate.
A method of forming a recessed gate transistor, the method comprising:
- forming a resist mask over a substrate, said resist mask exposing an active region formed in said substrate;
- implanting a first dopant species into said active region to a first depth;
- implanting a second dopant species into said active region to a second depth that is less than said first depth;
- forming a gate opening in said active region, said gate opening defining a bottom surface, wherein a depth of said bottom surface of said gate opening substantially corresponds to said second depth;
- and
- forming a gate insulation layer on said bottom surface.
A method of forming a recessed gate transistor, the method comprising:
- forming a gate opening defining a bottom surface in an active region formed in a substrate and having a first dopant species provided up to a first depth, and a second dopant species provided up to a second depth that is less than said first depth, wherein a depth of said bottom surface of said gate opening extends substantially to said second depth;
- forming a gate insulation layer on said bottom surface;
- forming a gate electrode in said gate opening above said gate insulation layer;
- and
- annealing said substrate to form source/drain regions and extension regions by diffusing said second dopant species.
Dependencies are inferred from the claim text.