Method of fabricating an ultra-narrow channel semiconductor device

A method of fabricating a nanowire having a comprising:

• depositing a nanowire on a first dielectric layer formed on a substrate, said nanowire having a first dimension;
• depositing a sacrificial dielectric layer over a first region of said nanowire and an etchable sacrificial layer over said sacrificial dielectric layer leaving exposed a second region and a third region of said nanowire, (said first region defining a channel region for said nanowire);
• depositing a first spacer on each side of said sacrificial dielectric layer and said etchable sacrificial layer;
• depositing a second dielectric layer over said first dielectric layer to cover said second region and third region;
• etching away said etchable sacrificial layer and said sacrificial dielectric layer;
• and
• thinning said first region of said nanowire by at least one thermal oxidation process and oxide removal process to thin said first region from said first dimension to a second dimension.

A method of fabricating an electronic device comprising depositing

• depositing a nanowire on a first dielectric layer formed on a substrate, said nanowire having a first dimension;
• depositing a sacrificial dielectric layer over a first region of said nanowire and an etchable sacrificial layer over said sacrificial dielectric layer leaving exposed a second region and a third region of said nanowire, said first region defining a channel region for said electronic device;
• depositing a first spacer on each side of said sacrificial dielectric layer and said etchable sacrificial layer;
• forming a source/drain region in each of said second region and said third region;
• depositing a second dielectric layer over said first dielectric layer to cover said second region and third region;
• etching away said etchable sacrificial layer and said sacrificial dielectric layer;
• thinning said first region of said nanowire by at least one thermal oxidation process and oxide removal process to thin said first region from said first dimension to a second dimension;
• and
• depositing a device gate stack over said first region, said device gate stack including a third dielectric layer and a gate electrode.