Gigabit ethernet performance monitoring
AssigneeApplied Micro Circuits Corporation
InventorsTimothy E. Giorgetta, Alan M. Sorgi, Daniel M. Castagnozzi
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Abstract
A method for analyzing Gigabit Ethernet (GBE) and fiber channel protocol communications is provided which provides a more detailed understanding of the errors, than that provided under the IEEE 802.3z standard. The method creates an additional parity error signal which is not specified under the IEEE 802.3z standard. The parity error signals and IEEE 802.3z invalid code word signals are used to provide an analysis of whether the underlying communication errors are a result of 8B/10B coding word errors or running disparity errors. A system and apparatus to monitor performance in accordance with the above-mentioned method is also provided.
Claims27
A method for measuring the performance of communications, the method comprising:
- receiving a first stream of information;
- evaluating the first stream of information with respect to the balanced distribution of logic states;
- and
- counting the number of imbalances in the distribution of logic states.
A performance monitor comprising:
- an error monitor circuit having a first input to accept code words for evaluation with respect to the balanced distribution of logic states, the error monitor circuit having at least a first output to provide signals indicating imbalances in the distribution of logic states;
- and
- an error count register having at least a first input connected to the output of the error monitor circuit, the error count register having a first output to provide a count of signals indicating imbalances in the distribution of logic states.
A performance monitoring system comprising:
- a transmitter providing a first stream of information arranged in a protocol selected from the group consisting of Gigabit Ethernet (GBE) and fiber optic channel communications;
- and
- a performance monitor including:
- an input connected to the output of the transmitter to receive the first information stream;
- an error monitor circuit having a first input connected to the input of the performance monitor to accept code words for evaluation with respect to the balanced distribution of logic states, the error monitor circuit having at least a first output to provide signals indicating imbalances in the distribution of logic states;
- and
- an error count register having at least a first input connected to the output of the error monitor circuit, the error count register having a first output to provide a count of signals indicating imbalances in the distribution of logic states.
Dependencies are inferred from the claim text.