Load/store micropacket handling system

A method comprising:

• interconnecting a compute node with a shared memory node;
• translating a processor instruction into an interconnect command, wherein translating the processor instruction into the interconnect command includes translating a processor store instruction into an interconnect write command;
• transforming the interconnect command into a direct memory access interconnect command;
• transmitting the direct memory access interconnect command via a link medium;
• performing an operation defined by the direct memory access interconnect command;
• and
• combining a plurality of interconnect write commands into a single direct memory access interconnect write command of a plurality of data elements.

A method comprising:

• interconnecting a compute node with a shared memory node;
• translating a processor instruction into an interconnect command;
• transforming the interconnect command into a direct memory access interconnect command;
• transmitting the direct memory access interconnect command via a link medium;
• and
• performing an operation defined by the direct memory access interconnect command;
• wherein the shared memory node modifies a memory address statically.

A method comprising:

• interconnecting a compute node with a shared memory node;
• translating a processor instruction into an interconnect command;
• transforming the interconnect command into a direct memory access interconnect command;
• transmitting the direct memory access interconnect command via a link medium;
• and
• performing an operation defined by the direct memory access interconnect command;
• wherein transforming the interconnect command into the direct memory access interconnect command includes transforming the interconnect read command into a direct memory access interconnect read command;
• and
• prefetching data with the compute node after translating the processor load instruction into the direct memory access interconnect read command.

An apparatus comprising:

• a computer network, including:
• a compute node, having:
• a compute node interconnect interface unit;
• and
• a compute node interconnect adapter;
• a link medium, coupled to the compute node;
• and
• a shared memory node, coupled to the link medium, having:
• a shared memory node interconnect interface unit;
• and
• a shared memory node interconnect adapter;
• wherein the compute node interconnect interface unit includes:
• a processor bus;
• a memory bus;
• an interconnect bus;
• a memory command translator;
• and
• a memory address translator;
• wherein the memory address translator includes a table of memory address ranges.

An apparatus comprising:

• a computer network, including:
• a compute node, having:
• a compute node interconnect interface unit;
• and
• a compute node interconnect adapter;
• a link medium, coupled to the compute node;
• and
• a shared memory node, coupled to the link medium, having:
• a shared memory node interconnect interface unit;
• and
• a shared memory node interconnect adapter;
• wherein the shared memory interconnect interface unit includes:
• a processor bus;
• a memory bus;
• an interconnect bus;
• a memory command translator;
• and
• a memory address translator;
• wherein the memory address translator includes a table of memory address ranges.

An apparatus comprising:

• a computer network, including:
• a compute node, having:
• a compute node interconnect interface unit;
• and
• a compute node interconnect adapter;
• a link medium, coupled to the compute node;
• and
• a shared memory node, coupled to the link medium, having:
• a shared memory node interconnect interface unit;
• and
• a shared memory node interconnect adapter;
• wherein the compute node interface adapter includes:
• an interconnect bus interface;
• an address translator;
• a speculative-read control register;
• a DMA-read control register;
• a link protocol generator;
• a link protocol responder;
• a receive buffer;
• a speculative-and-DMA read control calculator;
• and
• a speculative-read control exerciser.

An apparatus comprising:

• a computer network, including:
• a compute node, having:
• a compute node interconnect interface unit;
• and
• a compute node interconnect adapter;
• a link medium, coupled to the compute node;
• and
• a shared memory node, coupled to the link medium, having:
• a shared memory node interconnect interface unit;
• and
• a shared memory node interconnect adapter;
• wherein the shared memory node interconnect adapter, includes:
• an interconnect bus interface;
• an address translator;
• an interconnect read/write state machine;
• a link protocol generator;
• and
• a link protocol responder.