# US 6,890,778 B2 · Vertical cavity surface emitting laser and a method of fabrication thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,890,778 B2 - Document ID: US6890778B2 - Status: Granted - Kind: B2 - Application number: 10/382,372 - Filed: 2003-03-06 - Published: 2003-08-28 - Granted: 2005-05-10 - Earliest claimed: 2001-03-15 - Assignees: Epfl - Inventors: Elyahou Kapon; Vladimir Iakovlev; Alexei Sirbu; Alok Rudra - Web page: https://patentgrep.com/patent/US6890778B2 ## CPC - H01S 5/18308: {having a special structure for lateral current or light confinement} - B82Y 20/00: Nanooptics, e.g. quantum optics or photonic crystals - H01S 5/18316: {Airgap confined} - H01S 5/18341: {Intra-cavity contacts} - H01S 5/18358: {containing spacer layers to adjust the phase of the light wave in the cavity} - H01S 5/1838: {Reflector bonded by wafer fusion or by an intermediate compound} - H01S 5/18388: {Lenses} - H01S 5/2063: {obtained by particle bombardment} - H01S 5/3095: {Tunnel junction} - H01S 5/34306: {emitting light at a wavelength longer than 1000nm, e.g. InP based 1300 and 1500nm lasers} - H01S 5/4087: {emitting more than one wavelength} - H01S 5/423: {having a vertical cavity} - H01S: DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract An electrically pumped VCSEL and a method of its fabrication are presented. The VCSEL comprises an active cavity material sandwiched between top and bottom DBR stacks, the top DBR having at least one n-semiconductor layer. The device defines an aperture region between the structured surface of the active cavity material and the n-semiconductor layer of the top DBR stack. The structured surface is formed by a top surface of a mesa that includes at least the upper n++ layer of a p++/n++ tunnel junction and the surface of a p-type layer outside the mesa. The structured surface is fused to the surface of the n-semiconductor layer of the DBR stack due to the deformation of these surfaces, thereby creating an air gap in the vicinity of the mesa between the fused surfaces. The active region is defined by the current aperture which includes the mesa surrounded by the air gap, thereby allowing for restricting an electrical current flow to the active region, while the air gap provides for the lateral variation of the index of refraction in the VCSEL. ## Claims ### Claim 1 A method of fabrication of a vertical cavity surface emitting laser (VCSEL) device structure, the method comprising the steps of: (i) fabricating a semiconductor active cavity material structure including a multiquantum well (MQW) layer stack sandwiched between bottom and top spacer regions, the top spacer region terminating with a p-layer and a p++/n++ tunnel junction structure on top of said p-layer, each of the p++- and p-layers presenting a p-type layer, said active cavity material structure being patterned to form a mesa including at least the upper n++ layer of the tunnel junction emerging from the underlying p-type layer, and thereby having a structured surface formed by the upper surface of the mesa and the upper surface of the p-type layer outside the mesa; (ii) attaching the structured surface of the active cavity material structure to a substantially planar surface of a n-type semiconductor layer of a first Distributed Bragg Reflector (DBR) stack, thereby causing deformation of an attached surface around the mesa and defining an aperture region, that includes the mesa surrounded by an air gap between the deformed fused surfaces and defines an active region of the device; (iii) forming a second DBR stack on a surface of the active cavity material structure opposite to the structured surface; and (iv) forming ohmic contacts on the VCSEL device structure to enable the electrical current flow through the active region. ### Claim 2 (depends on 1) The method according to claim 1, wherein the active cavity material structure is grown on an InP substrate. ### Claim 3 (depends on 1) The method according to claim 1, wherein said tunnel junction is positioned at a minimum of a standing wave optical field in the device structure and has a thickness of about 20-50 nm. ### Claim 4 (depends on 1) The method according to claim 1, wherein the patterning comprises etching the mesa using a photoresist mask and is continued until the p-type layer is reached. ### Claim 5 (depends on 1) The method according to claim 1, wherein the patterning comprises etching the mesa using a photoresist mask and is continued until the p++ layer of the tunnel junction is reached. ### Claim 6 (depends on 1) The method according to claim 1, wherein said wafer fusion between the structured surface of the active cavity material structure and the surface of the first DBR stack comprises bringing these surfaces into face-to-face contact, and applying a pressure at elevated temperature. ### Claim 7 (depends on 6) The method according to claim 6, wherein pressure applied to the wafers that are in contact is varied at different stages of the fusion process. ### Claim 8 (depends on 7) The method according to claim 7, wherein, during purging at room temperature, a relatively low pressure is applied to the wafers and kept during a heating cycle till reaching a predetermined fusion temperature, followed by increasing pressure to a predetermined level. ### Claim 9 (depends on 8) The method according to claim 8, wherein said relatively low pressure applied during purging at room temperature does not exceed 0.5 bar/cm2, and the predetermined level of increased pressure is about 2.0 bar/cm2. ### Claim 10 (depends on 8) The method according to claim 8, wherein said predetermined fusion temperature is in the range of 550° C.-650° C. ### Claim 11 (depends on 8) The method according to claim 8, wherein the wafers are kept under the increased pressure for about 30 minutes. ### Claim 12 (depends on 1) The method according to claim 1, comprising formation of an electrical confining layer in the cavity material structure outside the mesa. ### Claim 13 (depends on 12) The method according to claim 12, wherein the formation of the electrical confining layer comprises ion implantation of the surface of the active cavity material structure outside the mesa, thereby creating an ion implanted current confining layer that reaches an outer boundary of the air-gap and is located outside the active region. ### Claim 14 (depends on 13) The method according to claim 13, wherein said ion implantation is carried out using photoresist discs as a mask, wherein the discs are located such as to be concentric with the mesa. ### Claim 15 (depends on 1) The method according to claim 1, comprising formation of at least one additional active region sandwiched between the first and second DBRs starting from said active cavity material structure, and formation of additional ohmic contacts on the VCSEL device structure to enable an electric current flow through the additional active region, said at least one additional active region including an additional mesa surrounded by an air gap between the fused structured surface of the active cavity material structure and the surface of the n-type semiconductor layer of the DBR stack. ### Claim 16 (depends on 15) The method according to claim 15, wherein the formation of said at least one additional active region comprises providing an additional n-type layer in the active cavity material structure, and carrying out said patterning of the active cavity material structure to form said at least one additional mesa terminating with said additional n-type layer. ### Claim 17 (depends on 16) The method according to claim 16, wherein said additional n-type layer has a thickness not exceeding ⅛ of the emission wavelength inside the VCSEL structure. ### Claim 18 (depends on 16) The method according to claim 16, wherein said patterning is carried out in a manner to form at least two additional mesas, each of the additional mesas containing a portion of said additional n-type layer of a thickness different to that of the other additional mesa. ### Claim 19 (depends on 1) The method according to claim 1, wherein both DBRs are made of AlAs and GaAs layers. ### Claim 20 (depends on 1) The method according to claim 1, wherein the second DBR stack is bonded to said surface of the active cavity material structure by wafer fusion. ### Claim 21 (depends on 1) The method according to claim 1, wherein the tunnel junction has a thickness ranging between 20 and 50 nm. ### Claim 22 (depends on 2) The method according to claim 2, wherein the active cavity material structure is fabricated by sequentially growing on an n-type InP substrate an InGaAsP-etch-stop layer, a bottom n-InP spacer layer, an undoped MQW layer stack, a top InP spacer layer terminating with a p-type InP layer, and the p++/n++ tunnel junction structure. ### Claim 23 (depends on 22) The method according to claim 22, wherein the p++ and n++ layers of the tunnel junction are, respectively, p++ InGaAs and n++ InGaAs layers. ### Claim 24 (depends on 22) The method according to claim 22, wherein the patterning to obtain the structured surface of the active cavity material structure comprises etching the mesa through the tunnel junction using a selective etching in a H3PO4:H2O2:H2O based solution. ### Claim 25 (depends on 24) The method according to claim 24, wherein the InP substrate is selectively etched in HCl till reaching the InGaAsP etch stop layer, and the InGaAsP etch stop layer is selectively etched in a H3PO4:H2O2:H2O solution. ### Claim 26 (depends on 1) The method according to claim 1, wherein the first DBR stack is grown on a GaAs-substrate by Metalo-Organic Chemical Vapor Deposition (MOCVD).