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US 6,889,357 B1Granted
Timing calibration pattern for SLDRAM
AssigneeMicron Technology, Inc.
InventorsBrent Keeth, Brian Johnson, Terry R. Lee, Paul M. Fuller
Life of this patent
Estimating the term…
Abstract
Disclosed is an improved start-up/reset calibration apparatus and method for use in an SLDRAM memory device A 2N bit calibration pattern which is based on a pseudo random sequence is used to calibrate the relative timing of data and a latching clock signal to ensure optimal operation of the memory device. In addition, during calibration of one data path, other nearby data paths may receive in phase, out of phase and/or both in phase and out of phase versions of the calibration pattern so that the data path under calibration is calibrated under conditions which more closely approximate random operating conditions.
Claims94
A device comprising:
- a memory;
- an input path for supplying data to said memory;
- and
- a pattern generator for generating a repeating bit pattern on said input path, said repeating bit pattern having an even number of bits, said pattern generator generating said repeating bit pattern by adding an additional bit to a pseudo random odd number bit pattern.
1 more element
A method of calibrating a digital circuit comprising:
- generating a repeating first calibration pattern for a period of time, said first calibration pattern having an even number of bit positions, said first calibration pattern containing an additional bit added to a pseudo random odd numbered bit pattern;
- applying said first calibration pattern to at least one digital signal path of said digital circuit;
- and
- using said applied first calibration pattern and a clock signal to adjust a delay element in said at least one signal path to a delay value which produces a reliable detection of said first calibration pattern.
1 more element
A digital circuit for calibrating incoming signal paths of a memory circuit, comprising:
- an incoming clock signal path;
- at least one incoming data signal path;
- at least one variable delay circuit, respectively provided in said incoming data signal path;
- at least one latch circuit, respectively coupled to the output of said variable delay circuit, said at least one latch circuit latching data in response to a clock signal on said incoming dock signal path;
- a pattern generation circuit, which generates a repeating bit pattern having an even number of bit positions on said at least one incoming data signal path;
- and
- a control logic circuit connected to receive an output of said latch circuit and connected to vary the delay of said delay circuit, said control logic circuit analyzing an output of said latch circuit and adjusting the delay of said variable delay circuit to synchronize data on said incoming data signal path with said dock signal.
4 more elements
A semiconductor memory circuit, comprising:
- a memory module;
- a memory controller connected to said memory module;
- and
- a calibration circuit for calibrating data incoming to said memory module, said calibration circuit comprising:
- an incoming clock signal path;
- at least one incoming data signal path;
- at least one variable delay circuit, respectively provided in said incoming data signal path;
- at least one latch circuit, respectively coupled to the output of said variable delay circuit, said at least one latch circuit latching data in response to a clock signal on said incoming clock signal path;
- a pattern generation circuit, which generates a repeating bit pattern having an even number of bit positions on said at least one incoming data signal path;
- and
- a control logic circuit connected to receive an output of said latch circuit and connected to vary the delay of said delay circuit, said control logic circuit analyzing an output of said latch circuit and adjusting the delay of said variable delay circuit to synchronize data on said incoming data signal path with said clock signal.
8 more elements
A processor-based system, comprising:
- a processor;
- an integrated memory circuit connected to said processor, said integrated memory circuit including a calibration circuit comprising:
- an incoming clock signal path;
- at least one incoming data signal path;
- at least one variable delay circuit, respectively provided in said incoming data signal path;
- at least one latch circuit, respectively coupled to the output of said variable delay circuit, said at least one latch circuit latching data in response to a clock signal on said incoming clock signal path;
- a pattern generation circuit, which generates a repeating bit pattern having an even number of bit positions on said at least one incoming data signal path;
- and
- a control logic circuit connected to receive an output of said latch circuit and connected to vary the delay of said delay circuit, said control logic circuit analyzing an output of said latch circuit and adjusting the delay of said variable delay circuit to synchronize data on said incoming data signal path with said clock signal.
6 more elements
An embedded-memory processor-based system, comprising:
- a processor;
- a memory circuit formed on a same integrated circuit as said processor, said memory circuit including a calibration circuit comprising:
- an incoming clock signal path;
- at least one incoming data signal path;
- at least one variable delay circuit, respectively provided in said incoming data signal path;
- at least one latch circuit, respectively coupled to the output of said variable delay circuit, said at least one latch circuit latching data in response to a clock signal on said incoming clock signal path;
- a pattern generation circuit, which generates a repeating bit pattern having an even number of bit positions on said at least one incoming data signal path;
- and
- a control logic circuit connected to receive an output of said latch circuit and connected to vary the delay of said delay circuit, said control logic circuit analyzing an output of said latch circuit and adjusting the delay of said variable delay circuit to synchronize data on said incoming data signal path with said clock signal.
6 more elements
Dependencies are inferred from the claim text.