Digital event sampling circuit and method

A circuit arrangement for sampling a plurality of digital event pulses, comprising:

• a first timer adapted to time a plurality of base time intervals;
• a second timer adapted to generate a sampling window signal for a sampling window time interval, the sampling window time interval being a shorter time than any of the base time intervals;
• a sample window initiate circuit coupled to the first timer and adapted to start the second timer at a pseudo-random time within each of the plurality of base time in intervals;
• and
• a sampler circuit coupled to the second timer and arranged to receive the plurality of digital event pulses and to pass a sample of digital event pulses responsive to the sampling window signal.

A method for sampling a logic data signal, comprising:

• receiving a plurality of digital event pulses characterizing the logic data signal during each of a series of base time intervals;
• applying a sampling window signal for a sample window time interval beginning at a pseudo-random time during each of a series of base time intervals;
• selecting a subset of digital event pulses during application of the sampling window signal;
• and
• accumulating a count of the subset digital event pulses.

A circuit arrangement to sample a logic data signal, comprising:

• means for receiving a plurality of digital event pulses characterizing the logic data signal during each of a series of base time intervals;
• means for applying a sampling window signal for a sample window time interval beginning at a pseudo-random time during each of a series of base time intervals;
• means for selecting a subset of digital event pulses during application of the sampling window signal;
• and
• means for accumulating a count of the subset digital event pulses.