Tester architecture construction data generating method, tester architecture constructing method and test circuit

A testing circuit for testing a semiconductor device constructed on the same semiconductor chip, comprising:

• a sequence controller which decodes an instruction code to thereby generate control signals in accordance with a predetermined order;
• an instruction storage unit which stores an instruction code to be supplied to said sequence controller;
• a testing signal generation/comparison unit which successively generates input signals and expected data signals for the semiconductor device to be tested, in accordance with the control signals produced from said sequence controller and compares each of signals outputted from the semiconductor device with said each expected data signal;
• and
• a testing signal timing generation unit which generates timings provided to input the signals to the semiconductor device to be tested in said testing signal generation/comparison unit in accordance with the control signals outputted from said sequence controller,
• wherein based on a compression ratio of the instruction code stored in said instruction storage unit, said testing signal generation/comparison unit and said testing signal timing generation unit are provided as circuits common to a plurality of signal input terminals of the semiconductor device to be tested, or circuits independent of one another in association with the respective signal input terminals of the semiconductor device, and
• said testing circuit is constructed within a variable logic circuit capable of constituting arbitrary logic on the semiconductor chip.

A construction data generating system for an architecture of a semiconductor device tester, comprising:

• a testing program having a plurality of functions corresponding to test contents of a semiconductor device to be tested by the semiconductor device tester, said testing program being described in a tester language;
• means for determining a configuration of a testing circuit having a test function necessary for testing of the semiconductor device, based on analysis by the testing program;
• and
• means for generating construction data of the testing circuit based on the determined configuration, thereby constructing the testing circuit within a variable logic circuit capable of constituting arbitrary logic.