Apparatus for improving output skew for synchronous integrate circuits has delay circuit for generating unique clock signal by applying programmable delay to delayed clock signal

A synchronous integrated circuit device, comprising:

• a clock input buffer configured to receive a system clock signal and to generate a buffered clock signal;
• a delay locked loop (DLL) coupled to the clock input buffer and configured to receive the buffered clock signal and to generate a delayed clock signal;
• an output circuit coupled to the DLL, the output circuit including a plurality of output signal paths configured to output the plurality of output signals synchronously with the system clock signal by using the delayed clock signal;
• wherein at least one of the output signal paths includes a delay circuit and an output buffer coupled to the delay circuit, each delay circuit configured to provide a programmable delay to the delayed clock signal to generate a unique delayed clock signal which is used for clocking an output signal into the respective output buffer;
• and
• wherein the programmable delay is set based upon feedback from others of the output signal paths to synchronize the output signal with other output signals.

A synchronous integrated circuit device, comprising:

• a clock input buffer configured to receive a system clock signal and to generate a buffered clock signal;
• a delay line coupled to the clock input buffer, the delay line configured to receive the buffered clock signal and to generate a delayed clock signal;
• an output circuit coupled to the delay line, the output circuit including a plurality of output signal paths configured to output the plurality of output signals synchronously with the system clock signal by using the delayed clock signal;
• wherein the output signal paths each includes a variable delay circuit and an output buffer coupled to the delay circuit, each delay circuit configured to provide an independent variable delay to the delayed clock signal to generate a unique delayed clock signal for clocking an output signal into the respective output buffer;
• and
• wherein each of the variable delay of each of the delay circuit is programmed based upon the delay of others of the plurality of output signals from other output buffers.

A method of outputting a plurality of output signals of a synchronous integrated circuit device with decreased output skew, comprising:

• receiving a system clock signal;
• delaying the system clock signal to generate a delayed clock signal;
• applying the delayed clock signal to a plurality of output signal paths;
• in each of the output signal paths, using the delayed clock signal to output the plurality of output signals synchronously with the system clock signal;
• and
• in at least one of the output signal paths, providing a programmable delay to the delayed clock signal to generate a unique delayed clock signal which is used for clocking an output signal out from the respective output signal path by determining the programmable delay based upon delay of the plurality of output signals.

A method of outputting a plurality of output signals on an output bus of a synchronous integrated circuit device with decreased output skew, comprising:

• receiving a system clock signal;
• delaying the system clock signal to generate a delayed clock signal;
• applying the delayed clock signal to a plurality of output signal paths;
• in each of the output signal paths, using the delayed clock signal to output the plurality of output signals synchronously with the system clock signal;
• in each of the plurality of output signal paths, providing an independent variable delay to the delayed clock signal to generate a unique delayed clock signal for use in clocking an output signal out from the respective output signal path;
• and
• determining the delay of each of the plurality of output signals to determine the independent variable delay for each of the plurality of output signal paths.

An apparatus for outputting an output signal on an output bus of a synchronous integrated circuit device with decreased output skew, comprising:

• an input circuit for receiving a system clock signal;
• a delay line coupled to the input circuit for delaying the system clock signal;
• an output circuit coupled to the delay line for outputting an output signal, the output circuit including a programmable delay circuit for providing a programmable delay to the delayed system clock signal for use in clocking out the output signal;
• and
• wherein the programmable delay is determined from an amount of delay of the output signals based upon feedback from s plurality of output signals.

An apparatus for outputting a plurality of output signals of a synchronous integrated circuit device with decreased output skew, comprising:

• an input circuit for receiving a system clock signal;
• a delay line coupled to the input circuit for delaying the system clock signal;
• an output circuit coupled to the delay line for outputting a plurality of data output signals,
• the output circuit including at least one programmable delay circuit for providing a programmable delay to the delayed system clock signal for use in clocking out at least one of the data output signals with decreased skew across an output bus;
• a feedback path is connected to the output circuit for receiving an amount of delay of the data output signals based;
• and
• a delay control circuit connected to the feedback path and to the programmable delay circuit for determining the programmable delay based upon the delay of the data output signals.