Memory controller receiver circuitry with tri-state noise immunity

Strobe receiver circuitry, comprising:

• a) a counter, said counter updating a count in response to strobe edges of received strobe signals;
• and
• b) counter control logic, said counter control logic enabling said counter before each strobe signal is received by generating start conditions asynchronously with respect to said received strobe signals;
• and said counter control logic resetting said counter after each strobe signal is received by i) receiving feedback from said counter, ii) generating stop conditions, and iii) in response to said feedback and stop conditions, resetting said counter asynchronously with respect to said received strobe signals.

Memory controller receiver circuitry, comprising:

• a) a data pad and a strobe pad;
• b) P storage elements coupled to receive data from said data pad (P≧2), said P storage elements being sequentially enabled to receive data by respective values of a count;
• c) a counter, said counter updating said count in response to strobe edges of received strobe signals;
• and
• d) counter control logic, said counter control logic enabling said counter before each strobe signal is received by generating control signals asynchronously with respect to said received strobe signals;
• and said counter control logic resetting said counter after each strobe signal is received by receiving feedback from said counter and, in response to said feedback, resetting said counter asynchronously with respect to said received strobe signals.

Memory controller receiver circuitry, comprising:

• a) a data pad and a strobe pad;
• b) P storage elements coupled to receive data from said data pad (P≧2), said P storage elements being sequentially enabled to receive data by respective values of a count;
• c) a counter, said counter updating said count in response to strobe edges of strobe signals received at said strobe pad;
• and
• d) counter control logic, said counter control logic enabling said counter before each strobe signal is received by generating start conditions asynchronously with respect to said received strobe signals;
• and said counter control logic resetting said counter after each strobe signal is received by i) receiving feedback from said counter, ii) generating stop conditions, and iii) in response to said feedback and stop conditions, resetting said counter asynchronously with respect to said received strobe signals.

A double data rate memory controller with tolerance for large variation in read loop delay, comprising:

• a) data receiving means;
• b) counting means for receiving and counting a number of strobe edges received during a memory read cycle;
• c) means for controlling said data receiving means in response to a count produced by said counting means;
• and
• d) means for enabling said counting means before each memory read cycle and resetting said counting means after each memory read cycle by i) enabling said counting means asynchronously with respect to said number of strobe edges, and ii) resetting said counting means asynchronously with respect to said number of strobe edges.

A method of receiving data into a memory controller, comprising, during a memory read cycle:

• a) enabling a counter asynchronously with respect to a strobe signal, before the strobe signal is received at a strobe pad, and in response to a start condition;
• b) storing sequential data bits received at a data pad in different ones of P storage elements (P≧2), in response to different values of a count produced by said counter;
• and
• c) resetting said counter asynchronously with respect to said strobe signal, after the strobe signal is received, and in response to a combination of counter feedback and a stop condition.

A computer system, comprising:

• a) a CPU;
• b) a memory controller coupled to said CPU;
• c) an I/O controller coupled to said CPU;
• d) a number of I/O devices coupled to said I/O controller;
• and
• e) a number of memory modules coupled to said memory controller;
• wherein said memory controller comprises a plurality of data and strobe pads to which are coupled receiver circuitry for receiving data and strobe signals from said memory modules;
• and
• wherein said receiver circuitry comprises, for corresponding data and strobe pads:
• i) P storage elements coupled to receive data from said data pad (P≧2), said P storage elements being sequentially enabled to receive data by respective values of a count;
• ii) a counter, said counter updating said count in response to strobe edges of strobe signals received at said strobe pad;
• and
• iii) counter control logic, said counter control logic enabling said counter before each strobe signal is received by generating start conditions asynchronously with respect to said received strobe signals;
• and said counter control logic resetting said counter after each strobe signal is received by i) receiving feedback from said counter, ii) generating stop conditions, and iii) in response to said feedback and stop conditions, resetting said counter asynchronously with respect to said received strobe signals.