Multimode system for calibrating a data strobe delay for a memory read operation
AssigneeAdvanced Micro Devices, Inc.
InventorsJames R. Magro, Bruce A. Loyer, Pratik M. Mehta
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AssigneeAdvanced Micro Devices, Inc.
InventorsJames R. Magro, Bruce A. Loyer, Pratik M. Mehta
Estimating the term…
A system for coordinating the timing of a data strobe with data supplied by a memory module to the memory controller read data FIFO of a processor-based system, providing multiple calibration modes. A calibration PDL (programmable delay line) is used to reiteratively test the time taken for a test data strobe to traverse a portion of the memory controller circuit, and to generate a calibration value based upon the time taken. The calibration procedure may be initiated in any one of several modes, including: according to a predetermined schedule; implemented in software; in response to changes in environmental factors such as temperature or voltages sampled at one or more locations; in response to a software-driven trigger; or in response to a user-initiated trigger, communicated to a system of the invention either by input via a user interface to the processor-based system or by a software command.
A multimode system for coordinating a data strobe with a data valid window in a read data operation over a data path from a memory module, including:
A method of operating a calibration subsystem of a memory controller of a processor-based system in multiple modes to coordinate a data strobe with a data valid window for a data read operation from a memory module, including the steps of:
A multimode circuit for coordinating arrival of a first signal and a second signal at a receiving device, where the second signal is coupled to a signal path, including:
Dependencies are inferred from the claim text.