Microprocessor with an instruction immediately next to a branch instruction for adding a constant to a program counter

A digital processing system comprising a microprocessor, wherein the microprocessor is operable to perform a method for forming a relative return address, the method comprising the steps of:

• fetching a sequence of instructions in response to address locations provided by a program counter;
• and
• executing a first instruction immediately after executing a branch-to-subroutine instruction in the sequence of instructions by using a first address value provided by the program counter as a source operand, said branch-to-subroutine instruction containing a plurality of delay slots, wherein said first instruction forms the relative return address, said relative return address associated with the branch-to-subroutine instruction, wherein said first instruction specifies a number of virtual no-operation (NOP) instructions to execute in the plurality of delay slots.

A method for calling a subroutine in a digital processing system comprising a microprocessor, the method comprising the steps of:

• branching to the subroutine by executing a first instruction to provide an address of the subroutine, said fist instruction containing a plurality of delay slots;
• and
• calculating a complete return address by executing a second instruction that is next to the first instruction to determine the return address, wherein no instructions separate the first and second instructions, said second instruction specifying a number of no-operation (NOP) instructions to execute in the plurality of delay slots.

A method for forming a relative return address in a digital processing system comprising a microprocessor, the method comprising the steps of:

• fetching a sequence of instructions in response to address locations provided by a program counter;
• and
• executing a first instruction immediately after executing a branch-to-subroutine instruction in the sequence of instructions by using a first address value provided by the program counter as a source operand, said branch-to-subroutine instruction containing a plurality of delay slots, wherein said first instruction forms the relative return address, said relative return address associated with the branch-to-subroutine instruction, wherein said first instruction specifies a number of virtual no-operation (NOP) instructions to execute in the plurality of delay slots.