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US 6,889,319 B1Granted
Method and apparatus for entering and exiting multiple threads within a multithreaded processor
AssigneeIntel Corporation
InventorsDion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu
Life of this patent
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Abstract
A method includes maintaining a state machine to provide a multi-bit output, each bit of the multi-bit output indicating a respective status for an associated thread of multiple threads being executed within a multithreaded processor. Status for a first thread is detected, responsive to which a functional unit within the multithreaded processor is configured in accordance with the multi-bit output of the state machine.
Claims33
A method including:
- maintaining a state machine to provide a multi-bit output, each bit of the multi-bit output indicating a respective status of an associated thread of multiple threads being executed with a multithreaded processor;
- detecting a change of status for a first thread within the multithreaded processor;
- and
- responsive to the change of status for the first thread within the multithreaded processor, configuring a functional unit within the multithreaded processor in accordance with the multi-bit output of the state machine, wherein the configuring of the functional unit within the multithreaded processor includes inserting a fence instruction into an instruction stream for the first thread at a location proximate a front-end of the multithreaded processor, the fence instruction defining an event boundary within the instruction stream that assumes all memory accesses have drained from the multithreaded processor.
1 more element
Apparatus including:
- a state machine to provide a multi-bit output, each bit of the multi-output indicating a respective status of an associated thread of multiple threads being executed within a multithreaded processor, and to detect a change of status for a first thread within the multithreaded processor;
- and
- configuration logic to configure a functional unit within the multithreaded processor in accordance with the multi-bit output of the state machine;
- and
- a microcode sequencer to introduce a fence instruction into an instruction stream for the first thread at a location proximate a front-end of the multithreaded processor, the fence instruction defining an event boundary within the instruction stream to ensure that all memory accesses drain from the multithreaded processor.
2 more elements
Apparatus comprising:
- first means for providing a multi-bit output, each bit of the multi-output indicating a respective status of an associated thread of multiple threads being executed within a multithreaded processor, and to detect a change of status for a first thread within the multithreaded processor;
- and
- second means for configuring a functional unit within the multithreaded processor in accordance with the multi-bit output of the state machine, wherein the configuring of the functional unit within the multithreaded processor includes inserting a fence instruction into an instruction stream for the first thread at a location proximate a front-end of the multithreaded processor, the fence instruction defining an event boundary within the instruction stream that assumes all memory accesses have drained from the multithreaded processor.
A machine-readable medium including a sequence of instructions that, when executed by a machine, cause the machine to:
- maintain a state machine to provide a multi-bit output, each bit of the multi-bit output indicating a respective status of an associated thread of multiple threads being executed with a multithreaded processor;
- detect a change of status for a first thread within the multithreaded processor;
- and
- configure a functional unit within the multithreaded processor in accordance with the multi-bit output of the state machine, wherein the configuring of the functional unit within the multithreaded processor includes inserting a fence instruction into an instruction stream for the first thread at a location proximate a front-end of the multithreaded processor, the fence instruction defining an event boundary within the instruction stream that assumes all memory accesses have drained from the multithreaded processor.
1 more element
Dependencies are inferred from the claim text.