Instruction fusion for digital signal processor
AssigneeLSI Logic Corporation
InventorShannon A. Wichman
Life of this patent
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Abstract
An instruction pipeline for a DSP with fusing logic for combining multiple instructions into a single control word which can be executed by one execution unit. The pipeline fetches a greater number of instructions than the number of execution units to which it can issue instructions. It applies grouping rules to the instructions and also identifies pairs, or larger groups, of instructions which can be combined, or fused, into a single control word which can be executed by one execution unit. Issuance of a fused control word to a single execution unit effectively allows two or more instructions to be executed simultaneously in one execution unit.
Claims41
A method for operating a pipeline in a processor comprising:
- fetching a number of unfused instructions, said number of fetched unfused instructions being greater than the number of execution units in a processor;
- and
- combining a plurality of the fetched unfused instructions into a control word which can be processed by one execution unit;
- wherein said processor has four execution units and said pipeline fetches at least five unfused instructions.
A processor comprising:
- an instruction pipeline having a first stage which fetches and decodes a number of unfused instructions, the number of unfused instructions fetched and decoded by said first stage being greater than the number of execution units in said processor, and
- fusing logic in a second stage of said pipeline combining a plurality of said decoded unfused instructions into a control word which can be executed by one execution unit.
A system for coupling instructions from memory to execution units in a processor comprising;
- fetching means for fetching and decoding a number of unfused instructions, the number of unfused instructions fetched and decoded by said fetching means being greater than the number of execution units in said processor, and
- fusing means for combining a plurality of said fetched and decoded unfused instructions into a control word which can be executed by one execution unit.
A method for operating a pipeline in a processor comprising:
- fetching a number of unfused instructions, said number of fetched unfused instructions being greater than the number of execution units in a processor;
- combining a plurality of the fetched unfused instructions into a control word which can be processed by one execution unit;
- and
- returning unfused instructions which cannot be combined and processed by one execution unit;
- wherein said returned unfused instructions are included in a next fetching of a number of unfused instructions greater than the number of execution units in a processor.
Dependencies are inferred from the claim text.