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US 6,889,317 B2Granted
Processor architecture
AssigneeSTMicroelectronics S.r.l.
InventorsMariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Danilo Pau, Roberto Zafalon
Life of this patent
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Abstract
An architecture for a pipeline processor circuit, preferably of the VLIW type, comprises a plurality of stages and a network of forwarding paths which connect pairs of said stages, as well as a register file for operand write-back. An optimization-of-power-consumption function is provided via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network on account of their reduced liveness length.
Claims58
An architecture for a pipeline processor, comprising:
- a plurality of stages;
- a forwarding network of forwarding paths which connect said stages;
- and
- a register file for operand write-back, wherein one of said stages includes an optimization-of-power-consumption function via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network because of reduced liveness lengths of said operands, wherein said function is configured for performing selectively, for a register of said register file assigned by a first instruction comprising a write-back stage and used by a second instruction, the following:
- disabling of write-back of said register in said register file in the write-back stage of said first instruction;
- and
- inhibiting assertion of a read address of said register in said register file by said second instruction.
4 more elements
An architecture for a pipeline processor, comprising:
- a plurality of stages;
- a forwarding network of forwarding paths which connect said stages;
- and
- a register file for operand write-back, wherein one of said stages includes an optimization-of-power-consumption function via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network because of reduced liveness lengths of said operands, wherein said one of said stages includes dedicated logic for disabling the write-enable signals that enable writing in said register file, wherein the one of said stages is a decoding stage for decoding the instructions and reading the operands from said register file, and said dedicated logic is included in said decoding stage.
1 more element
An architecture for a pipeline processor, comprising:
- a plurality of stages;
- a forwarding network of forwarding paths which connect said stages;
- a register file for operand write-back, wherein one of said stages includes an optimization-of-power-consumption function via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network because of reduced liveness lengths of said operands;
- and
- dedicated logic which minimizes read-port switching activity in said register file by maintaining values on the input read addresses of the register file at previous clock cycles.
2 more elements
An architecture for a pipeline processor, comprising:
- a plurality of stages;
- a forwarding network of forwarding paths which connect said stages;
- a register file for operand write-back, wherein one of said stages includes an optimization-of-power-consumption function via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network because of reduced liveness lengths of said operands;
- and
- interstage registers coupled between stages of the plurality of stages, including latch registers used as a memory layer for storing the operands, wherein said interstage registers are not write-addressable, in so far as they are implicitly addressed.
2 more elements
An architecture for a pipeline processor, comprising:
- a plurality of stages;
- a forwarding network of forwarding paths which connect said stages;
- a register file for operand write-back, wherein one of said stages includes an optimization-of-power-consumption function via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network because of reduced liveness lengths of said operands;
- and
- interstage registers coupled between stages of the plurality of stages, including latch registers used as a memory layer for storing the operands, wherein said interstage registers are configured as a transient memory which cannot be associated to a machine state that can be saved in the event of an exception, wherein said architecture is configured in such a way that sequences of instructions that use said interstage registers are treated as atomic sequences that are not subject to interrupts.
2 more elements
An architecture for a pipeline processor, comprising:
- a plurality of stages;
- a forwarding network of forwarding paths which connect said stages;
- a register file for operand write-back, wherein one of said stages includes an optimization-of-power-consumption function via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network because of reduced liveness lengths of said operands wherein said processor is a superscalar processor comprising a hardware control unit capable of analyzing an instruction window to determine liveness lengths of registers of the register file;
- interstage registers coupled between stages of the plurality of stages, including latch registers used as a memory layer for storing the operands, wherein said interstage registers are configured as a transient memory which cannot be associated to a machine state that can be saved in the event of an exception;
- and
- a function of generation of two pseudo-instructions, one for checkpoint declaration and one for checkpoint release, with the provision of a shadow register, wherein a program counter is saved from an instant of checkpoint declaration, a machine state not being modifiable until checkpoint release, whereby, upon checkpoint release, the shadow register is reset and the interrupts are disabled atomically.
3 more elements
Dependencies are inferred from the claim text.