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US 6,889,316 B2Granted
Method and apparatus for restoring registers after cancelling a multi-cycle instruction
AssigneesIntel Corporation, Analog Devices, Inc.
InventorsRyo Inoue, Gregory A. Overkamp
Life of this patent
Estimating the term…
Abstract
In an embodiment, a pipelined processor may be adapted to process multi-cycle instructions (MCIs). Results generated in response to non-terminal sub-instructions may be written to a speculative commit register. When the MCI commits, i.e., a terminal sub-instruction reaches the WB stage, the value in the speculative commit register may be written to the architectural register.
Claims24
A method comprising:
- introducing a multi-cycle instruction including two or more sub-instructions into multiple stages of a pipeline;
- writing a result generated in response to a sub-instruction in a speculative commit register;
- and
- writing a value in the speculative commit register to an architectural register in response to the multi-cycle instruction committing, wherein the committing occurs when a last sub-instruction of the multi-cycle instruction reaches a write back stage of the pipeline.
1 more element
An article comprising a machine-readable medium which stores machine-executable instructions, the instructions causing a machine to:
- introduce a multi-cycle instruction including two or more sub-instructions into multiple stages of pipeline;
- write a result generated in response to a sub-instruction in a speculative commit register;
- and
- write a value in the speculative commit register to an architectural register in response to the multi-cycle instruction committing, wherein the committing occurs when a last sub-instruction of the multi-cycle instruction reaches a write back stage of the pipeline.
1 more element
A processor comprising:
- a pipeline operative to execute a multi-cycle instruction including a terminal sub-instruction and a non-terminal sub-instruction;
- an architectural register;
- a speculative commit register operative to store results generated in response to the sub-instructions;
- and
- a controller operative to control writing a result from the speculative commit register to the architectural register in response to the terminal sub-instruction committing, wherein the committing occurs when the terminal sub-instruction of the multi-cycle instruction reaches a write back stage of the pipeline.
2 more elements
A system comprising:
- a static random address memory;
- and
- a processor coupled to the static random access memory, said processor comprising:
- a pipeline operative to execute a multi-cycle instruction including a terminal sub-instruction and a non-terminal sub-instruction;
- an architectural register;
- a speculative commit register operative to store results generated in response to the sub-instructions;
- and
- a controller operative to control writing a result from the speculative commit register to the architectural register in response to the terminal sub-instruction committing, wherein the committing occurs when the terminal sub-instruction of the multi-cycle instruction reaches a write back stage of the pipeline.
5 more elements
Dependencies are inferred from the claim text.