Processor and method of controlling the same

A processor that executes programmed instructions, comprising:

• a storage destination memory unit that stores a storage designation of a result obtained by executing a second instruction prior to execution of a first instruction, the second instruction being placed after the first instruction in a program;
• a judgment unit that determines whether an address of first data to be processed by the first instruction is included in an address region of second data to be processed by the second instruction;
• a data restoration unit that overwrites a result obtained by executing the first instruction on the second data corresponding to the address of the first data at the storage destination stored in the storage destination memory unit, when the judgment unit determines that the address of the first data is included in the address region of the second data
• a storage unit that stores data, where the first instruction is a store instruction to store the first data into the storage unit, and the second instruction is a load instruction to read out the second data from the storage unit.

A method of controlling a processor that controls execution of programmed instructions arranged in a program, the method comprising:

• executing an instruction prior to execution of a branch instruction, the instruction being placed after the branch instruction in the program;
• retaining an exception operation when necessity of the exception operation is detected in execution;
• performing the exception operation when the retained exception operation is needed in execution of an instruction at a branch destination selected through the execution of the branch instruction by a commit instruction;
• and
• returning to the program so as to continue the execution of the instruction at the branch destination when the exception operation is finished.

A method of controlling a processor that controls execution of instructions arranged in a program, the method comprising:

• executing an instruction prior to execution of a branch instruction, the instruction being placed after the branch instruction in the program;
• retaining an exception operation when an exception start instruction that requires the exception operation is detected during the executing;
• performing the exception operation when the retained exception operation is required in execution of an instruction at a branch destination selected through the execution of the branch instruction by a commit instruction;
• and
• returning to the program so as to sequentially execute the instructions starting from the exception start instruction, when the exception operation is finished.

A processor that executes instructions arranged in a program, the processor comprising:

• a control unit that controls an execution sequence so that an instruction placed after a branch instruction in the program is executed prior to execution of the branch instruction;
• an exception inhibiting unit that retains an exception operation when necessity of the exception operation is detected during the execution of the instruction placed after the branch instruction;
• an exception operation unit that performs the exception operation when the exception operation retained by the exception inhibiting unit is needed in execution of an instruction at a branch destination selected through execution of the branch instruction by a commit instruction;
• and
• a return unit that returns to the program when the exception operation is finished, and continues the execution of the instruction at the branch destination.

A processor that executes instructions arranged in a program, the processor comprising:

• a control unit that controls an execution sequence so that an instruction placed after a branch instruction in the program is executed prior to execution of the branch instruction;
• an exception inhibiting unit that retains an exception operation when an exception start instruction that requires the exception operation is detected during the execution of the instruction placed after the branch instruction;
• an exception operation unit that performs the exception operation when the exception operation retained by the exception inhibiting unit is needed in execution of an instruction at a branch destination selected through execution of the branch instruction by a commit instruction;
• and
• a return unit that returns to the program when the exception operation is finished, and sequentially executes the instructions starting from the exception start instruction.

A method of controlling execution of instructions in a program, the method comprising:

• executing an instruction prior to execution of a branch instruction, the instruction being placed after the branch instruction in the program;
• retaining a break operation when necessity to suspend execution of the program is detected in executing the instruction by an exception inhibiting load instruction;
• and
• performing the break operation when the retained break operation is required in execution of an instruction at a branch destination selected through the execution of the branch instruction.