Method and apparatus for fast dependency coordinate matching
AssigneeIntel Corporation
InventorsNicholas G. Samra, Murali S. Chinnakonda
Life of this patent
Estimating the term…
Abstract
Disclosed herein is a method for matching dependency coordinates and an efficient apparatus for performing the dependency coordinate matching very quickly. A plurality of buffers to store instructions is set forth. Each storage location of a buffer corresponds to a particular pair of dependency coordinates. Dependency matching logic receives the dependency coordinates for a buffered instruction and scheduling information pertaining to dispatched instructions. The dependency matching logic indicates whether a dependency precludes scheduling of the corresponding buffered instruction. Dependency checking logic produces a ready signal for the buffered instruction when no such dependency is indicated by the dependency matching logic.
Claims29
An apparatus comprising:
- dependency matching logic to receive a first dependency coordinate and a second dependency coordinate corresponding to a single dependency relationship, the dependency matching logic, upon receiving the first and second dependency coordinates, to identify whether the dependency precludes scheduling;
- and
- dependency checking logic to produce a ready signal if the dependency matching logic has not identified that scheduling is precluded.
A method for scheduling an instruction for execution comprising:
- generating a first dependency coordinate to indicate that a second instruction is dependent on a first instruction;
- generating a second dependency coordinate to indicate that the second instruction is dependent on the first instruction;
- dispatching the first instruction for execution;
- using the first dependency coordinate to access the second dependency coordinate in response to the first instruction being dispatched;
- and
- dispatching the second instruction after accessing the second dependency coordinate.
A method for scheduling an instruction for execution comprising:
- storing a first instruction in a first location within a first buffer;
- storing a second instruction, dependent on the first instruction, in a second location within a second buffer;
- generating a first dependency coordinate for the second instruction to indicate that the second instruction is dependent on an instruction stored in the first buffer;
- and
- generating a second dependency coordinate for the second instruction to indicate that the second instruction is dependent on an instruction stored in the first location.
A dependency matching logic comprising:
- a first storage location to store a first dependency coordinate referencing one of a plurality of operation buffers;
- a second storage location to store a second dependency coordinate referencing a location of a plurality of addressable locations in an operation buffer;
- an interface to receive an indication of a first scheduled operation, the dependency matching logic, upon receiving the indication of the first scheduled operation, to identify whether the first scheduled operation corresponds to the location referenced by the second dependency coordinate in the buffer referenced by the first dependency coordinate.
A dependency matching logic comprising:
- means for storing a first dependency coordinate referencing one of a plurality of operation buffers;
- means for storing a second dependency coordinate referencing a location of a plurality of addressable locations in an operation buffer;
- means for receiving an indication of a first scheduled operation;
- and
- means for identifying whether the first scheduled operation corresponds to the location referenced by the second dependency coordinate in the buffer referenced by the first dependency coordinate.
An article of manufacture comprising:
- a machine-accessible medium including data that, when accessed by a machine, cause the machine to:
- generate a first dependency coordinate for a first instruction to indicate that the first instruction is dependent on an instruction stored in a first buffer;
- generate a second dependency coordinate for the first instruction to indicate that the first instruction is dependent on an instruction stored in a first location in a buffer;
- match the first dependency coordinate to a dispatching of a second instruction from the first buffer;
- match the second dependency coordinate to a dispatching of the second instruction from the first location in the first buffer;
- and
- dispatch the second instruction after matching the first dependency coordinate and the second dependency coordinate.
A computing system comprising:
- dependency coordinate logic to store a first dependency coordinate referencing one of a plurality of operation buffers and a second dependency coordinate referencing a location of a plurality of addressable locations in an operation buffer;
- dispatch logic coupled to the dependency coordinate logic to send an indication of a first scheduled operation;
- dependency match logic to identify whether the first scheduled operation corresponds to the location referenced by the second dependency coordinate in the buffer referenced by the first dependency coordinate.
Dependencies are inferred from the claim text.