Selection of decoder output from two different length instruction decoders
AssigneeSTMicroelectronics S.r.l.
InventorsAndrew Cofler, Stéphane Bouvier, Laurent Wojcieszak
Life of this patent
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Abstract
A decode unit comprises first and second decoders respectively connected to receive bit sequences of first and second predetermined lengths. The first and second decoders operate in parallel to generate respective outputs. A switch selects one of the outputs in dependence on an instruction mode of the processor which governs the length of the bit sequence which is actually required to be decoded.
Claims18
A decode unit for decoding instructions in a processor each instruction comprising a bit sequence having one of a first or second predetermined length depending on one of a plurality of instruction modes of the processor, the decode unit comprising:
- a first decoder having an input connected to receive a first bit sequence of the first predetermined length and operating on receipt of said fist bit sequence to generate a first decoded output;
- a second decoder having an input connected to receive a second bit sequence of the second predetermined length different from the first predetermined length and operating on receipt of said second bit sequence to generate a second decoded output;
- a communication path for supplying said first bit sequence to the first decoder while simultaneously supplying said second bit sequence to the second decode;
- and
- switching circuitry responsive to an instruction mode signal specifying an instruction mode of the plurality of instruction modes, to select one of the first and second decoded outputs in dependence on the specified instruction mode.
A method of decoding instructions in a processor, each instruction comprising a bit sequence having one of a first or second length depending on one of the plurality of instruction modes of the processor, the method comprising:
- decoding a bit sequence of the first predetermined length and generating a first decoded output;
- simultaneously decoding a bit sequence of the second predetermined length different than the first predetermined length and generating a second decoded output;
- and
- selecting one of the first and second decoded outputs responsive to an instruction mode signal specifying an instruction mode of the plurality of instruction modes.
A decode unit for decoding instructions in a processor, the instructions comprising a bit sequence having a length depending on an instruction mode of the processor, the decode unit comprising:
- a first decoder having an input connected to receive a bit sequence of a first predetermined length and operating on receipt of said bit sequence to generate a first decoded output;
- a second decoder having an input connected to receive a bit sequence of a second predetermined length and operating on receipt of said bit sequence to generate a second decoded output;
- a communication path for supplying a bit sequence simultaneously to said first and second decoders;
- and
- switching circuitry, responsive to an instruction mode signal, to select one of the first and second outputs in dependence on the instruction mode of the processor;
- a third decoder having an input connected to receive a bit sequence of the second predetermined length and operating on receipt of said bit sequence to generate a third decoded output, wherein the second predetermined length is half the first predetermined length;
- an input buffer for holding a bit sequence of the first predetermined length and simultaneously supplying said bit sequence to the first decoder and to each of the second and third decoders;
- a fourth decoder having an input connected to receive a bit sequence of said first predetermined length and operating on receipt of said bit sequence to generate a fourth decoded output, the decode unit further comprising switching circuitry responsive to the instruction mode signal to select one of the third and fourth outputs in dependence on the specified instruction mode;
- and
- a second input buffer for holding a bit sequence of the first predetermined length and for supplying said bit sequence to the fourth decoder,
- wherein the switching circuitry and further switching circuitry operate so that, the first and fourth decoded outputs are simultaneously selected, or the second and third decoded outputs are simultaneously selected.
A processor comprising:
- at least one execution unit for executing instructions;
- an instruction mode indicator which indicates one of a plurality of instruction modes for the processor;
- a decode unit for decoding instructions prior to dispatch to the at least one execution unit;
- and
- an instruction supply mechanism for supplying instructions to the decode unit, wherein said instructions are represented by bit sequences, each bit sequence having one of a first and second predetermined length depending on an instruction mode of the plurality of the instruction modes of the processor, and
- wherein the decode unit comprises:
- a first decoder having an input connected to receive a first bit sequence of a first predetermined length and operating on receipt of said first bit sequence to generate a first decoded output;
- a second decoder having an input connected to receive a second bit sequence of a second predetermined length different from the first predetermined length and operating on receipt of said second bit sequence to generate a second decoded output;
- a communication path for supplying said first bit sequence to the first decoder while simultaneously supplying said second bit sequence to the second decoder;
- and
- switching circuitry, responsive to an instruction mode signal specifying an instruction mode of the plurality of instruction modes, to select one of the first and second decoded outputs in dependence on the specified instruction mode.
Dependencies are inferred from the claim text.