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US 6,889,312 B1Granted
Selective zero extension based on operand size
AssigneeAdvanced Micro Devices, Inc.
InventorsKevin J. McGrath, Ramsey W. Haddad, Bruce R. Holloway, I-Cheng K. Chen
Life of this patent
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Abstract
A processor supports multiple operand sizes (e.g. 8, 16, 32, and 64 bit operand sizes, in one embodiment). Additionally, the processor determines how to update a destination register when an operand size less than the largest operand size is used. In one embodiment, the processor determines whether or not to zero extend the result responsive to the operand size used. In one particular embodiment, the processor zero extends 32 bit operands and does not zero extend 8 or 16 bit operands. Furthermore, the processor may preserve the value in at least part of the remaining portion of the register when 8 or 16 bit operand sizes are used.
Claims28
A processor comprising:
- a register configured to store a first number of bits;
- and
- an execution core coupled to said register, wherein said execution core is configured to execute an instruction to produce a result, said instruction having said register as a destination, and wherein said execution core is configured to zero extend said result for update in said register responsive to an operand size corresponding to said instruction specifying a second number of bits less than said first number of bits, and wherein said execution core is configured to preserve a value of at least a portion of said bits in said register that are not updated by said result responsive to said operand size specifying a third number of bits less than said first number of bits and different from said second number.
A computer-implemented method-comprising:
- executing an instruction to produce a result, said instruction having a register as a destination and said register configured to store a first number of bits;
- zero extending said result for update in said register responsive to an operand size corresponding to said instruction specifying a second number of bits less than said first number of bits;
- and
- preserving a value of at least a portion of said bits in said register that are not updated by said result responsive to said operand size specifying a third number of bits less than said first number of bits and different from said second number.
1 more element
An apparatus comprising
- a storage location corresponding to a register, said register defined to store a first number of bits;
- and
- an execution circuit coupled to said storage location, wherein said execution circuit is configured to execute an instruction to produce a result, said instruction having said register as a destination, and wherein said execution core is configured to zero extend said result for update in said storage location responsive to an operand size corresponding to said instruction specifying a second number of bits less than said first number of bits, and wherein said execution circuit is configured to preserve a value of at least a portion of said bits in said storage location that are not updated by said result responsive to said operand size specifying a third number of bits less than said first number of bits and different from said second number.
An apparatus comprising:
- a storage location corresponding to a register, said register defined to store a first number of bits;
- and
- an execution circuit coupled to said storage location, wherein said execution circuit is configured to execute an instruction to produce a result, said instruction having said register as a destination, and wherein said execution core is configured to extend said result to said first number of bits for update in said storage location responsive to an operand size corresponding to said instruction specifying a second number of bits less than said first number of bits, and wherein said execution circuit is configured to preserve a value of at least a portion of said bits in said storage location that are not updated by said result responsive to said operand size specifying a third number of bits less than said first number of bits and different from said second number.
A computer system comprising:
- a processor comprising a register configured to store a first number of bits and an execution core coupled to said register, wherein said execution core is configured to execute an instruction to produce a result, said instruction having said register as a destination, and wherein said execution core is configured to zero extend said result for update in said register responsive to an operand size corresponding to said instruction specifying a second number of bits less than said first number of bits, and wherein said execution core is configured to preserve a value of at least a portion of said bits in said register that are not updated by said result responsive to said operand size specifying a third number of bits less than said first number of bits and different from said second number;
- and
- an input/output (I/O) device configured to communicate between said computer system and another computer system.
A computer system comprising:
- a processor comprising a register configured to store a first number of bits and an execution core coupled to said register, wherein said execution core is configured to execute an instruction to produce a result, said instruction having said register as a destination, and wherein said execution core is configured to extend said result to said first number of bits for update in said register responsive to an operand size corresponding to said instruction specifying a second number of bits less than said first number of bits, and wherein said execution core is configured to preserve a value of at least a portion of said bits in said register that are not updated by said result responsive to said operand size specifying a third number of bits less than said first number of bits and different from said second number;
- and
- an input/output (I/O) device configured to communicate between said computer system and another computer system.
Dependencies are inferred from the claim text.