Pipeline stage single cycle sliding alignment correction of memory read data with integrated data reordering for load and store instructions
AssigneeTexas Instruments Incorporated
InventorsJose L. Flores, Lewis Nardini
Life of this patent
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Abstract
Trace data is aligned in a processor having an instruction pipeline by delaying write data and read data a predetermined number of clock cycles, selectively swapping both most significant write data and read data with least significant write data and read dependent upon memory access control data. The write and read data pass normally for even memory bank accesses and are swapped for odd memory bank accesses. Memory access control data, program counter data and program counter control data are similarly delayed. At least the read data and optionally all the data are held upon a pipeline stall.
Claims11
A method for trace data alignment in a processor having an instruction pipeline comprising the steps of:
- delaying write data a predetermined number of clock cycles;
- selectively swapping most significant write data and least significant write data dependent upon memory access control data;
- delaying read data the predetermined number of clock cycles;
- and
- selectively swapping most significant read data and least significant read data dependent upon memory access control data,
- wherein:
- said steps selectively swapping write data selectively swapping read data swap the write data and read data when the memory access control data indicates memory access to an odd memory bank.
An apparatus for trace data alignment in a processor having an instruction pipeline comprising:
- a predetermined number of cascade write data clock delay registers having an input receiving write data and an output delayed the predetermined number of clock cycles;
- a first multiplexer having a first input receiving most significant bits from one of said cascade write data clock delay registers, a second input receiving least significant bits from said one of said cascade write data clock delay registers, a control input and an output supplying a selected one of the first input or the second input to most significant bit input of a next cascade write data clock delay register dependent upon a signal at said control input;
- a second multiplexer having a first input receiving least significant bits from said one of said cascade write data clock delay registers, a second input receiving most significant bits from said one of said cascade write data clock delay registers, a control input and an output supplying a selected one of the first input or the second input to least significant bit input of a next cascade write data clock delay register dependent upon a signal at said control input;
- said predetermined number of cascade read data clock delay registers having an input receiving read data and an output delayed the predetermined number of clock cycles;
- a third multiplexer having a first input receiving most significant bits from one of said cascade read data clock delay registers, a second input receiving least significant bits from said one of said cascade read data clock delay registers, a control input and an output supplying a selected one of the first input or the second input to most significant bit input of a next cascade read data clock delay register dependent upon a signal at said control input;
- a fourth multiplexer having a first input receiving least significant bits from said one of said cascade read data clock delay registers, a second input receiving most significant bits from said one of said cascade read data clock delay registers, a control input and an output supplying a selected one of the first input or the second input to least significant bit input of a next cascade read data clock delay register dependent upon a signal at said control input;
- and
- a shift correction circuit having an input receiving memory access control data and an output connected to said control inputs of said first, second, third and fourth multiplexers controlling said selection of said first, second, third and fourth multiplexers.
Dependencies are inferred from the claim text.